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authorLijian Zhao <lijian.zhao@intel.com>2017-10-19 11:55:29 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-20 20:52:46 +0000
commit6a09eee4ade53d31e966ee9ca4c531e4dc9aea73 (patch)
tree59fb680f12f53008f417101e81b13954f5cc8087 /src/superio/smsc/sio10n268
parent418535e222ccd9f688facbb7d9663ca4cacc2739 (diff)
soc/intel/cannonlake: Add platform.asl
Include common platform.asl to have generic indication of power transition state of system. TEST=Enter and resume from S3, check the post code had been changed to 0096 and 0097. Change-Id: Ic38ac6d7e60441caeba5c088c9dbe4d901355782 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22111 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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