diff options
| author | Michael Büchler <michael.buechler@posteo.net> | 2020-08-02 15:38:10 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-08-10 12:44:17 +0000 |
| commit | a815272b7b9dbf23ac170ec6c7ec44093cd52406 (patch) | |
| tree | 412fa100dc58d01a3271270cc0bdc04c8e7c4efa /src/superio/ite/common | |
| parent | e693b1d549621acfd20aaad876d4d5888ad5ca99 (diff) | |
superio/ite: allow 24 MHz clock for external sensor interface
The interface selection register of the environment controller (EC)
gives the choice between "Internal generated 32 MHz" and "24 MHz" for
the "SST/PECI Host Controller Clock Selection".
Previously the chip was always configured for the 32 MHz clock. Add an
option that can be set from devicetree.cb to allow using the 24 MHz
clock.
Without this setting the automatic fan control on an Acer Aspire M3800
was slow to respond to temperature changes.
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: Ib2bce10a828fb4a7d837f6c5f5b1d00cc51be0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44166
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/superio/ite/common')
| -rw-r--r-- | src/superio/ite/common/env_ctrl.c | 7 | ||||
| -rw-r--r-- | src/superio/ite/common/env_ctrl_chip.h | 5 |
2 files changed, 12 insertions, 0 deletions
diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index fbf74468b0..8668110713 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -264,6 +264,13 @@ void ite_ec_init(const u16 base, const struct ite_ec_config *const conf) ITE_EC_INTERFACE_SMB_ENABLE); } + /* Set SST/PECI Host Controller Clock to either 24 MHz or internal 32 MHz */ + if (conf->smbus_24mhz) { + pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT, + pnp_read_hwm5_index(base, ITE_EC_INTERFACE_SELECT) | + ITE_EC_INTERFACE_CLOCK_24MHZ); + } + /* Enable reading of voltage pins */ pnp_write_hwm5_index(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index 09577a4d84..fa896e4074 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -91,6 +91,11 @@ struct ite_ec_config { * Enable SMBus for external thermal sensor. */ bool smbus_en; + /* + * Select 24 MHz clock for external host instead of an + * internally generated 32 MHz clock. + */ + bool smbus_24mhz; }; /* Some shorthands for device trees */ |