Restructure i3100 Super I/O driver to match the rest of the codebase.

 - i3100_early_serial.c:

    - Split out enter/exit functions as the other Super I/Os do.

    - Make i3100_enable_serial() take a device_t as usual, and convert
      it to use the standard pnp_* function instead of open-coding
      the same functionality by hand.

    - Factor out i3100_configure_uart_clk() from i3100_enable_serial(),
      we do the same in various other Super I/Os, e.g. ITE ones.

 - Add some #defines for register / bit values and some comments.

 - Only functional change: Don't set bit 1 of SIW_CONFIGURATION, it's
   marked as "READ ONLY, WRITES IGNORED" in the datasheet.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 38 insertions, 20 deletions

diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h
index f0d6426be0..6218e6d09f 100644
--- a/src/superio/intel/i3100/i3100.h
+++ b/src/superio/intel/i3100/i3100.h
@@ -46,6 +46,19 @@
 #define I3100_SP2 0x05 /* Com2 */
 #define I3100_WDT 0x06 /* Watchdog timer */
 
-#define I3100_SUPERIO_CONFIG_PORT 0x4e
+/* Registers and bit definitions: */
+
+#define I3100_SIW_CONFIGURATION		0x29
+
+/*
+ * SIW_CONFIGURATION[3:2] = UART_CLK predivide
+ * 00: divide by 1
+ * 01: divide by 8
+ * 10: divide by 26
+ * 11: reserved
+ */
+#define I3100_UART_CLK_PREDIVIDE_1	0x00
+#define I3100_UART_CLK_PREDIVIDE_8	0x01
+#define I3100_UART_CLK_PREDIVIDE_26	0x02
 
 #endif
diff --git a/src/superio/intel/i3100/i3100_early_serial.c b/src/superio/intel/i3100/i3100_early_serial.c
index 74c20c537c..23f8cab5ab 100644
--- a/src/superio/intel/i3100/i3100_early_serial.c
+++ b/src/superio/intel/i3100/i3100_early_serial.c
@@ -21,31 +21,36 @@
 #include <arch/romcc_io.h>
 #include "i3100.h"
 
-static void i3100_sio_write(u8 port, u8 ldn, u8 index, u8 value)
+static void pnp_enter_ext_func_mode(device_t dev)
 {
-	outb(0x07, port);
-	outb(ldn, port + 1);
-	outb(index, port);
-	outb(value, port + 1);
-}
+	u16 port = dev >> 8;
 
-static void i3100_enable_serial(u8 port, u8 ldn, u16 iobase)
-{
-	/* Enter configuration state. */
 	outb(0x80, port);
 	outb(0x86, port);
+}
 
-	/* Enable serial port. */
-	i3100_sio_write(port, ldn, 0x30, 0x01);
-
-	/* Set serial port I/O region. */
-	i3100_sio_write(port, ldn, 0x60, (iobase >> 8) & 0xff);
-	i3100_sio_write(port, ldn, 0x61, iobase & 0xff);
-
-	/* Enable device interrupts, set UART_CLK predivide to 26. */
-	i3100_sio_write(port, 0x00, 0x29, 0x0b);
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+	u16 port = dev >> 8;
 
-	/* Exit configuration state. */
 	outb(0x68, port);
 	outb(0x08, port);
 }
+
+/* Enable device interrupts, set UART_CLK predivide. */
+static void i3100_configure_uart_clk(device_t dev, u8 predivide)
+{
+	pnp_enter_ext_func_mode(dev);
+	pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1);
+	pnp_exit_ext_func_mode(dev);
+}
+
+static void i3100_enable_serial(device_t dev, u16 iobase)
+{
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+	pnp_exit_ext_func_mode(dev);
+}