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authorLijian Zhao <lijian.zhao@intel.com>2018-07-31 17:23:32 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-09-28 09:53:01 +0000
commitb269f873b0a0d43911adc907a53bbebadc742b78 (patch)
tree23e53691cef9dcfd19d63d8128e28638699aae97 /src/southbridge
parent80346d04906261b258e1f7ea737a74beac08b11a (diff)
soc/intel/cannonlake: Update UPD from device switch
Some of the FSP silicon UPD entry can be updated base on device switch in pci device tree, have both static config setting and device tree "on" and "off" will be redundant. BUG=N/A TEST=Build and boot up fine with Whiskey Lake RVP platform. Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27766 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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