diff options
| author | Ronald G. Minnich <rminnich@gmail.com> | 2004-09-30 16:37:22 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2004-09-30 16:37:22 +0000 |
| commit | a4779e80c3e54e6e6c31169908803065b4ef68b2 (patch) | |
| tree | 80dc6721ec07d14523e6ed3ee1af30013f869a6b /src/southbridge | |
| parent | 2b763af4ca6541734ff7d36a16173f9606c248c9 (diff) | |
digital logic stuff, fixes for the smbus code in 82801dbm
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c b/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c index de721a1e83..05ad2d7b5c 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c +++ b/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c @@ -46,6 +46,21 @@ static inline void smbus_delay(void) outb(0x80, 0x80); } +static int smbus_wait_until_active(void) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if ((val & 1)) { + break; + } + } while(--loops); + return loops?0:-4; +} + static int smbus_wait_until_ready(void) { unsigned long loops; @@ -112,7 +127,10 @@ static int smbus_read_byte(unsigned device, unsigned address) /* start a byte read, with interrupts disabled */ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - + /* poll for it to start */ + if (smbus_wait_until_active() < 0) { + return -4; + } /* poll for transaction completion */ if (smbus_wait_until_done() < 0) { |