diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-09 19:12:35 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-11-11 02:47:23 +0100 |
| commit | 22dfccf5b78ba87b015172200de0356648172210 (patch) | |
| tree | af0b58635cff925fce3971341a7b0881a7a0f320 /src/southbridge | |
| parent | f89a05ed9f7307df32ef5fa1fd558db7f594c269 (diff) | |
southbridge/amd/sb700: Disable broken SATA MSI functionality
Change-Id: I4e0a52eb90910604f8640ad7533b5d71be6c8e20
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11983
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/sb700/early_setup.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 4a38294603..145215a15d 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -658,6 +658,7 @@ static void sb700_pci_cfg(void) { device_t dev; u8 byte; + uint8_t acpi_s1_supported = 1; /* SMBus Device, BDF:0-20-0 */ dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); @@ -710,10 +711,10 @@ static void sb700_pci_cfg(void) byte = pci_read_config8(dev, 0x40); byte |= 1 << 0; pci_write_config8(dev, 0x40, byte); - if (get_sb700_revision(pci_locate_device(PCI_ID(0x1002, 0x4385), 0)) <= 0x12) - pci_write_config8(dev, 0x34, 0x70); /* set 0x61 to 0x70 if S1 is not supported. */ + if (acpi_s1_supported) + pci_write_config8(dev, 0x34, 0x70); /* Hide D3 power state and MSI capabilities */ else - pci_write_config8(dev, 0x34, 0x50); /* set 0x61 to 0x50 if S1 is not supported. */ + pci_write_config8(dev, 0x61, 0x70); /* Hide MSI capability */ byte &= ~(1 << 0); pci_write_config8(dev, 0x40, byte); } |