diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2017-02-16 11:45:19 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-20 04:44:13 +0100 |
| commit | ee6a612eb2edb32a55ee92c6fdfcdc474c6b21f1 (patch) | |
| tree | 58e6ea542f08ca957da9a5462ae0e286d70d2d3a /src/southbridge | |
| parent | efd9dee646629948a54f68eca21b6ee922c55e10 (diff) | |
Revert "intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano"
We've been able to narrow down the problem to a single register/
single bit, so revert this commit and address the problem in a
follow-on commit.
This reverts commit 0f2025da0fd4dce6b951b4c4b97c9370ca7d66db.
Change-Id: I780f9ea2976dd223aaa3e060aef6e1af8012c346
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18384
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/Kconfig | 9 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 2 |
2 files changed, 0 insertions, 11 deletions
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 31a7db3fa2..742f95cbd2 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -97,13 +97,4 @@ config LOCK_MANAGEMENT_ENGINE bool default n -config LYNXPOINT_POWER_OPTIMIZER - bool "Enable Power Optimizer" - default y if CHROMEOS - help - Enable the power optimizer for the High Speed I/O - Power Control (HSIOPC). This can break graphics - under Windows, but can improve battery life under - 'mostly idle' conditions. - endif diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a399eb357a..04cb0bd504 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -346,7 +346,6 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = { RCBA_RMW_REG_32(0x33b4, 0, 0x00007001), RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff), RCBA_RMW_REG_32(0x3354, 0, 0x00000001), -#if IS_ENABLED(CONFIG_LYNXPOINT_POWER_OPTIMIZER) RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */ RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080), /* Power Optimizer */ RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */ @@ -354,7 +353,6 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = { RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */ RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */ RCBA_RMW_REG_32(0x3a80, 0, 0x05145005), -#endif RCBA_END_CONFIG }; |