diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-10-17 17:00:26 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-07-11 18:08:04 +0200 |
| commit | 6dbbe2ee96406db44b8e890d315e6704eecef8b1 (patch) | |
| tree | 243e4a8ba9f228ee13d3694b117a0a189a91629f /src/southbridge | |
| parent | 32d2e2b3608006b615521eb68f011aa72f44171e (diff) | |
intel/lynxpoint: Allow to always route USB3 ports to XHCI
This will make USB keyboards connected to USB3 ports work
in libpayload on Beltino.
BUG=chrome-os-partner:23396
BRANCH=none
TEST=Use USB keyboard on Beltino in dev mode screen
Change-Id: I70b03d733bd9e4c8be5673b48bd2196effa8a5e7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173640
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
[pm: rebase to master branch of coreboot upstream]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6018
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/chip.h | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/usb_xhci.c | 6 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index e47a0310be..cc2cda0210 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -111,6 +111,9 @@ struct southbridge_intel_lynxpoint_config { * [24] = CLKOUT_ITPXDP */ uint32_t icc_clock_disable; + + /* Route USB ports to XHCI per default */ + uint8_t xhci_default; }; extern struct chip_operations southbridge_intel_lynxpoint_ops; diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 997ef61098..6c7bf046a8 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -26,6 +26,8 @@ #include <arch/io.h> #include "pch.h" +typedef struct southbridge_intel_lynxpoint_config config_t; + static u32 usb_xhci_mem_base(device_t dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -294,6 +296,7 @@ static void usb_xhci_init(device_t dev) u32 reg32; u16 reg16; u32 mem_base = usb_xhci_mem_base(dev); + config_t *config = dev->chip_info; /* D20:F0:74h[1:0] = 00b (set D0 state) */ reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); @@ -356,6 +359,9 @@ static void usb_xhci_init(device_t dev) /* Reset ports that are disabled or * polling before returning to the OS. */ usb_xhci_reset_usb3(dev, 0); + } else if (config->xhci_default) { + /* Route all ports to XHCI */ + outb(0xca, 0xb2); } } |