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| author | Werner Zeh <werner.zeh@siemens.com> | 2021-07-23 13:09:41 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-29 09:14:05 +0000 |
| commit | 0b39a5a23ac8eb06b06757b94f641151d8603c10 (patch) | |
| tree | 60724ea9ebd5a4fea6fc0e8d1f4ff9f3a94a45cd /src/southbridge | |
| parent | cf35fd37482f750fffb087920185c05f95031f1b (diff) | |
mb/siemens/mc_ehl1: Disable LTR for all PCIe root ports
Latency Tolerance Reporting is yet another PCIe power management feature
which can have a bad influence on realtime performance. Disable this
feature for all PCIe root ports.
Change-Id: I38023e095ca55efd2178ad944f651fee1f1c34cd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions