sb,soc/intel: Set IOAPIC redirection entry count

The number of redirection table entries (aka interrupt vectors) inside
an I/O APIC may depend of the SKU, with the related register being of
type read/write-once. Provide support utilities to either lock or set
this registers value.

Change-Id: I8da869ba390dd821b43032e4ccbc9291c39e6bab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

5 files changed, 10 insertions, 33 deletions

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index dfebaf0dac..b1f5ec8430 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -37,8 +37,6 @@ typedef struct southbridge_intel_bd82x6x_config config_t;
  */
 static void pch_enable_ioapic(struct device *dev)
 {
-	u32 reg32;
-
 	/* Assign unique bus/dev/fn for I/O APIC */
 	pci_write_config16(dev, LPC_IBDF,
 		PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
@@ -46,8 +44,7 @@ static void pch_enable_ioapic(struct device *dev)
 	set_ioapic_id(VIO_APIC_VADDR, 0x02);
 
 	/* affirm full set of redirection table entries ("write once") */
-	reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
-	io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
+	ioapic_lock_max_vectors(VIO_APIC_VADDR);
 }
 
 static void pch_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 866ede9a50..21f1faa3b7 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -27,20 +27,13 @@ typedef struct southbridge_intel_i82801ix_config config_t;
 
 static void i82801ix_enable_apic(struct device *dev)
 {
-	u32 reg32;
-	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
-	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
-
 	/* Enable IOAPIC. Keep APIC Range Select at zero. */
 	RCBA8(0x31ff) = 0x03;
 	/* We have to read 0x31ff back if bit0 changed. */
 	RCBA8(0x31ff);
 
 	/* Lock maximum redirection entries (MRE), R/WO register. */
-	*ioapic_index	= 0x01;
-	reg32		= *ioapic_data;
-	*ioapic_index	= 0x01;
-	*ioapic_data	= reg32;
+	ioapic_lock_max_vectors(VIO_APIC_VADDR);
 
 	setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */
 }
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index 69990ab8ba..106669d883 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -28,20 +28,13 @@ typedef struct southbridge_intel_i82801jx_config config_t;
 
 static void i82801jx_enable_apic(struct device *dev)
 {
-	u32 reg32;
-	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
-	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
-
 	/* Enable IOAPIC. Keep APIC Range Select at zero. */
 	RCBA8(0x31ff) = 0x03;
 	/* We have to read 0x31ff back if bit0 changed. */
 	RCBA8(0x31ff);
 
 	/* Lock maximum redirection entries (MRE), R/WO register. */
-	*ioapic_index	= 0x01;
-	reg32		= *ioapic_data;
-	*ioapic_index	= 0x01;
-	*ioapic_data	= reg32;
+	ioapic_lock_max_vectors(VIO_APIC_VADDR);
 
 	setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */
 }
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index c14c6a28b1..f1cf7a3b7f 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -34,12 +34,10 @@ typedef struct southbridge_intel_ibexpeak_config config_t;
  */
 static void pch_enable_ioapic(struct device *dev)
 {
-	u32 reg32;
-
 	set_ioapic_id(VIO_APIC_VADDR, 0x01);
+
 	/* affirm full set of redirection table entries ("write once") */
-	reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
-	io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
+	ioapic_lock_max_vectors(VIO_APIC_VADDR);
 }
 
 static void pch_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index d0eb4b33f0..ef75d2f77d 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -31,8 +31,6 @@
  */
 static void pch_enable_ioapic(struct device *dev)
 {
-	u32 reg32;
-
 	/* Assign unique bus/dev/fn for I/O APIC */
 	pci_write_config16(dev, LPC_IBDF,
 		PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
@@ -40,13 +38,11 @@ static void pch_enable_ioapic(struct device *dev)
 	set_ioapic_id(VIO_APIC_VADDR, 0x02);
 
 	/* affirm full set of redirection table entries ("write once") */
-	reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
-	if (pch_is_lp()) {
-		/* PCH-LP has 39 redirection entries */
-		reg32 &= ~0x00ff0000;
-		reg32 |= 0x00270000;
-	}
-	io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
+	/* PCH-LP has 40 redirection entries */
+	if (pch_is_lp())
+		ioapic_set_max_vectors(VIO_APIC_VADDR, 40);
+	else
+		ioapic_lock_max_vectors(VIO_APIC_VADDR);
 }
 
 static void pch_enable_serial_irqs(struct device *dev)