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| author | Ben Gardner <gardner.ben@gmail.com> | 2016-03-04 16:42:08 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-07 04:24:57 +0100 |
| commit | 2ae9cce87a9aee32b465a50d8ea3bb888c97eb68 (patch) | |
| tree | bedcf8d7e0b637eac21ecd4770dc06b6f88f6583 /src/southbridge | |
| parent | fba78bf8972b2fbc9e9089bc41226dcc79953804 (diff) | |
intel/fsp_baytrail: use 20K PU/PD for GPIO
The E3800 datasheet only lists 2K and 20K Pull Strength for the GPIOs.
The 10K and 40K values map to 'reserved'.
This brings the code closer to the non-FSP baytrail.
Change-Id: I77078bdbbccc00976525dc43fb98f5b2e79eae03
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/13907
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions