Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 8 insertions, 8 deletions

diff --git a/src/southbridge/via/k8t890/k8t890_bridge.c b/src/southbridge/via/k8t890/k8t890_bridge.c
index e30cf60b4d..3e1e81730d 100644
--- a/src/southbridge/via/k8t890/k8t890_bridge.c
+++ b/src/southbridge/via/k8t890/k8t890_bridge.c
@@ -32,14 +32,14 @@ static void bridge_enable(struct device *dev)
 	writeback(dev, 0x40, 0x91);
 	writeback(dev, 0x41, 0x40);
 	writeback(dev, 0x43, 0x44);
-	writeback(dev, 0x44, 0x31); 	/* K8M890 should have 0x35 datasheet 
-					 * says it is reserved 
+	writeback(dev, 0x44, 0x31); 	/* K8M890 should have 0x35 datasheet
+					 * says it is reserved
 					 */
 	writeback(dev, 0x45, 0x3a);
 	writeback(dev, 0x46, 0x88);	/* PCI ID lo */
 	writeback(dev, 0x47, 0xb1);	/* PCI ID hi */
 
-	/* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP 
+	/* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP
 	 * (Forward VGA compatible memory and I/O cycles )
 	 */
 
diff --git a/src/southbridge/via/k8t890/k8t890_ctrl.c b/src/southbridge/via/k8t890/k8t890_ctrl.c
index ad17fe624d..48aa739257 100644
--- a/src/southbridge/via/k8t890/k8t890_ctrl.c
+++ b/src/southbridge/via/k8t890/k8t890_ctrl.c
@@ -23,7 +23,7 @@
 #include <device/pci_ids.h>
 #include <console/console.h>
 
-/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate 
+/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
  * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
  */
 
diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c
index 0505a6ff5a..037f5a75eb 100644
--- a/src/southbridge/via/k8t890/k8t890_early_car.c
+++ b/src/southbridge/via/k8t890/k8t890_early_car.c
@@ -38,7 +38,7 @@ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
 
 /* This functions sets KT890 link frequency and width to same values as
  * it has been setup on K8 side, by AMD NB init.
- */ 
+ */
 
 u8 k8t890_early_setup_ht(void)
 {
@@ -115,7 +115,7 @@ u8 k8t890_early_setup_ht(void)
 
 static int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 {
-	
+
 	printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
 	switch (size) {
 	case 1:
diff --git a/src/southbridge/via/k8t890/k8t890_host_ctrl.c b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
index 38f69680fe..a1c42b7d59 100644
--- a/src/southbridge/via/k8t890/k8t890_host_ctrl.c
+++ b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
@@ -52,7 +52,7 @@ static void host_ctrl_enable_k8t890(struct device *dev)
 	pci_write_config8(dev, 0xa6, 0x80);
 
 	/* this will be possibly removed, when I figure out
-	 * if the ROM SIP is good, second reason is that the 
+	 * if the ROM SIP is good, second reason is that the
 	 * unknown bits are AGP related, which are dummy on K8T890
 	 */
 
diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc
index 9642aa4d5c..aaaa76694d 100644
--- a/src/southbridge/via/k8t890/romstrap.inc
+++ b/src/southbridge/via/k8t890/romstrap.inc
@@ -48,7 +48,7 @@ tblpointer:
 .long 0x0
 .long 0x0
 .long 0x0
-.long 0x0 
+.long 0x0
 
 /*
  * The pointer to above table should be at 0xffffd,