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| author | Subrata Banik <subrata.banik@intel.com> | 2018-02-20 11:49:45 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-02-22 09:56:37 +0000 |
| commit | e83d057c3ec3b9a34503008439275777849c0c6a (patch) | |
| tree | ab7e04792cf134c70382f1356b7486abfde10366 /src/southbridge/sis/sis966/sata.c | |
| parent | f9eaede51848d28214b47ade110b20ceac8a53e2 (diff) | |
soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode
TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree.
Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/sis/sis966/sata.c')
0 files changed, 0 insertions, 0 deletions