diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2019-04-08 17:14:36 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-11 11:28:09 +0000 |
| commit | 7fc25c013b91f26933705549d65e29b0301ff51d (patch) | |
| tree | e672d96e174b3329eb217cbab3d873ca51f1f409 /src/southbridge/intel | |
| parent | 67d630945ba6d70b630065f1a4dd8ce8a67ae5d2 (diff) | |
mb/google/sarien: Reserve gpio pins for D3 cold control
Based on HW change, reserve gpio pins for D3 cold control.
A13,A15 for Card reader
H13 for M.2 SSD
BUG=b:123263562
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions