diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-08-21 13:16:21 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-07-04 17:50:20 +0200 |
| commit | 78145a56b4f0332804d3b843f0ca855821308d83 (patch) | |
| tree | edb4661399a676f020f1dff9909f556261a77efd /src/southbridge/intel | |
| parent | 7034b9ef77c8e3782eb920f602ef962a38f221a3 (diff) | |
intel/lynxpoint: Use separate SMI callback for USB XHCI routing
This will allow the legacy mode boot path to leave USB
ports routed to EHCI so they can be used by SeaBIOS.
BUG=chrome-os-partner:22085
BRANCH=falco,peppy
TEST=manual: Build and boot from USB and SeaBIOS on falco
Change-Id: I46870eccd1b846dc8a7f8d7948969c8e623e18cd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6011
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/smihandler.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index d1e9bbc7cd..00e4a839f4 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -316,10 +316,8 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; - case APM_CNT_FINALIZE: -#if CONFIG_FINALIZE_USB_ROUTE_XHCI + case 0xca: usb_xhci_route_all(); -#endif break; #if CONFIG_ELOG_GSMI case ELOG_GSMI_APM_CNT: |