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authorAngel Pons <th3fanbus@gmail.com>2021-01-06 02:40:14 +0100
committerAngel Pons <th3fanbus@gmail.com>2021-01-10 15:42:05 +0000
commit78c45bd3ef775a790f5cfe60462d37d5edb19e4f (patch)
treeb5a864347b3c68216b95ff60e5cec900ea2ee642 /src/southbridge/intel
parent732eaf20c3319ec3558ff3333efc8ff87f7115de (diff)
sb/intel/bd82x6x: Use `PCH_LPC_DEV` macro
Change-Id: I681bb126546b5a7bda3f1bac05c345d2cf60b178 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/smihandler.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 1a9e5b4252..f0929f494c 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -70,7 +70,7 @@ void southbridge_gate_memory_reset(void)
{
u16 gpiobase;
- gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
+ gpiobase = pci_read_config16(PCH_LPC_DEV, GPIOBASE) & 0xfffc;
if (!gpiobase)
return;