summaryrefslogtreecommitdiff
path: root/src/southbridge/intel
diff options
context:
space:
mode:
authorArchana Patni <archana.patni@intel.com>2015-12-18 23:38:21 +0530
committerPatrick Georgi <pgeorgi@google.com>2016-02-04 17:44:28 +0100
commit6c1bf27daee6470fb35383dd180bc9b4cb368eab (patch)
treed3a8be2fa275c75f2c9a309e8b71c915dd0e3ccc /src/southbridge/intel
parent50c3ba24d4969aa33454325abe1a4a25ef4bcc94 (diff)
intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown
Keeping ACPI PM timer alive prevents XTAL OSC shutdown in S0ix which has a power impact. Based on a DT variable, this patch disables the ACPI PM timer late in the boot sequence - disabling earlier will lead to a hang since the FSP boot flow needs this timer. This also hides the ACPI PM timer from the OS by removing from FADT table. Once the ACPI PM timer is disabled, TCO gets switched off as well. BRANCH=none BUG=chrome-os-partner:48646 TEST=Build for skylake board with the PmTimerDisabled policy in devicetree set to 1. iotools mmio_read32 0xfe0000fc should return 0x2. cat /sys/devices/system/clocksource/clocksource0/available_clocksource should list only "tsc hpet". acpi_pm should be removed from this list. Change-Id: Icfdc51bc33b5190a55196d67e18afdaaa2f9b310 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 18bcb8a434b029295e1f1cc925e2b47e79254583 Original-Change-Id: Ifebe8bb5a7978339e07e4e12e174b9b978135467 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319361 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13588 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions