diff options
| author | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2015-07-07 12:57:46 -0500 |
|---|---|---|
| committer | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2015-07-14 13:40:07 +0200 |
| commit | ec505ad21c923c114a16b2710a0113f657765430 (patch) | |
| tree | c3ecdb6021982e2d79220b63d40448bebe43baf2 /src/southbridge/intel/sch/Makefile.inc | |
| parent | fb4233bb22602c3802da39200b85845407e0c496 (diff) | |
azalia: fix up and clean up shrinkage of boilerplate code
Should fix regression in HDA verb setup on nvidia mcp55 and intel sch
southbridges. The mcp55 code could not find the mainboard's verb table
because the table was not even being compiled in. The sch boards appeared
to have the same issue.
Intel broadwell and fsp_bd82x6x seemed to have not gotten the boilerplate
shrink, so apply it to those too.
Followup-to: Ib3e09644c0ee71aacb067adaa85653d151b52078
(azalia: Shrink boilerplate)
Change-Id: If7aae69f5171db67055ffe220bdff392caaa5d9f
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10826
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/sch/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/sch/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/sch/Makefile.inc b/src/southbridge/intel/sch/Makefile.inc index db876a15d8..0b21801f2b 100644 --- a/src/southbridge/intel/sch/Makefile.inc +++ b/src/southbridge/intel/sch/Makefile.inc @@ -36,6 +36,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c # We don't ship that, but booting without it is bound to fail cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin |