Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board

which uses it.

Compiles, but not boot tested lately.
Many things missing (eg. SMM support, proper ACPI, ...)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 32 insertions, 0 deletions

diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig
new file mode 100644
index 0000000000..525db06dc5
--- /dev/null
+++ b/src/southbridge/intel/sch/Kconfig
@@ -0,0 +1,32 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config SOUTHBRIDGE_INTEL_SCH
+	bool
+	select TINY_BOOTBLOCK
+	select HAVE_USBDEBUG
+
+config EHCI_BAR
+	hex
+	default 0xfef00000 if SOUTHBRIDGE_INTEL_SCH
+
+config EHCI_DEBUG_OFFSET
+	hex
+	default 0xa0 if SOUTHBRIDGE_INTEL_SCH
+