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| author | Karthikeyan Ramasubramanian <kramasub@chromium.org> | 2022-02-14 23:34:24 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-17 21:43:29 +0000 |
| commit | e1d6f5b80d58cf6a87b69d95477e2dfe3889a6e3 (patch) | |
| tree | c2046dcc8a8f92f6b56da52c6df324b98c0aef27 /src/southbridge/intel/lynxpoint/iobp.h | |
| parent | 3248db0e5a060271d7c1e87c4b687bec0b6c8d97 (diff) | |
util/spd_tools/spd_gen/lp5: Encode Bank Architecture
ADL supports 8B Bank Architecture, whereas Sabrina supports either BG or
16B Bank Architectures depending on the speed. This influences SDRAM
Density and Banks, SDRAM Addressing bytes in SPD. Encode them as per the
individual SoC advisories.
BUG=b:211510456
TEST=Generate SPDs for Sabrina.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic854ccccb2b301e75d0f28cd36daf87fd41e07e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/iobp.h')
0 files changed, 0 insertions, 0 deletions