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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-07 23:54:15 +1000
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-08 13:53:21 +0200
commit264d265d9c0f9f6c157fcc12d28b238849d25293 (patch)
tree126f0c4f4d01f92e66ecb4c296d5035d09d57f74 /src/southbridge/intel/i82870
parent730e3b02fb30b944664f69d9a73e69256bc9952f (diff)
southbridge: Trivial - drop trailing blank lines at EOF
Change-Id: I5484ebb665453777cc3b2561be6e50c787f1a257 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6209 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82870')
-rw-r--r--src/southbridge/intel/i82870/82870.h1
-rw-r--r--src/southbridge/intel/i82870/pci_parity.c2
-rw-r--r--src/southbridge/intel/i82870/pcibridge.c1
3 files changed, 0 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h
index b869de67b0..b576cc1beb 100644
--- a/src/southbridge/intel/i82870/82870.h
+++ b/src/southbridge/intel/i82870/82870.h
@@ -12,4 +12,3 @@
#define STRP_HPCAP 0x0002 // Hot-plug capable (Hx_SLOT zero/nonzero)
#define ACNF_SYNCPH 0x0010 // PCI(-X) input clock is synchronous to hub input clock
-
diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c
index fe27abf280..71d2c538e9 100644
--- a/src/southbridge/intel/i82870/pci_parity.c
+++ b/src/southbridge/intel/i82870/pci_parity.c
@@ -21,5 +21,3 @@ void p64h2_pci_parity_enable(void)
return;
}
-
-
diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c
index 89b86f5966..b46b3381ab 100644
--- a/src/southbridge/intel/i82870/pcibridge.c
+++ b/src/southbridge/intel/i82870/pcibridge.c
@@ -36,4 +36,3 @@ static const struct pci_driver pcix_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82870_1F0,
};
-