diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2017-07-03 21:35:58 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2017-07-06 08:49:25 +0000 |
| commit | ddb64d33a0c4e005a30092960953707b12fd78c6 (patch) | |
| tree | 1d2e9ed298adb8a2fbeb3e4a59938677095be3ae /src/southbridge/intel/i82801gx/smi.c | |
| parent | 43927bae1846e0768cbfad717f4820f408cde82b (diff) | |
sb/intel/i82801gx: Add whitespace around '<<'
Change-Id: I8ea8fdb031c09aac9ed4a0705c3204f87aadb565
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/smi.c')
| -rw-r--r-- | src/southbridge/intel/i82801gx/smi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index 45fcb10307..17a81c1757 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -232,9 +232,9 @@ static u32 reset_tco_status(void) reg32 = inl(tcobase + 0x04); /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS + outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS if (reg32 & (1 << 18)) - outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS + outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS return reg32; } |