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authorElyes Haouas <ehaouas@noos.fr>2022-03-06 15:36:00 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-04-29 14:41:09 +0000
commit09106f75f1c196d97fbc5fa998bfe1e602091266 (patch)
tree51887ea97b6683fd0918403453141f8c1d3bf8c9 /src/southbridge/intel/i82801dx
parent9f15a6c031fac884d934ab65b3d06d1ae37ed9b5 (diff)
sb/intel/i82801dx/pci.c: Use pci_or_config16() and macros
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I658fa9cee4517b9f68102b74949d32d7ab0309f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801dx')
-rw-r--r--src/southbridge/intel/i82801dx/pci.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82801dx/pci.c b/src/southbridge/intel/i82801dx/pci.c
index 2cc1b9d478..77437056b9 100644
--- a/src/southbridge/intel/i82801dx/pci.c
+++ b/src/southbridge/intel/i82801dx/pci.c
@@ -8,13 +8,8 @@
static void pci_init(struct device *dev)
{
- /* Enable pci error detecting */
- uint32_t dword;
/* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1 << 8); /* SERR# Enable */
- dword |= (1 << 6); /* Parity Error Response */
- pci_write_config32(dev, 0x04, dword);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
}
static struct device_operations pci_ops = {