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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-08 11:31:19 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-10 19:10:42 +0000 |
| commit | d165357ec37ce89ff4ee05f6d0bcfac6e766c1df (patch) | |
| tree | 70e3d2bcc856b7ec458b98561d485de538293da5 /src/southbridge/intel/i82801dx | |
| parent | c0457358f6ac47f8a771af474bb1987c74fb0cd6 (diff) | |
sb,soc/intel: Use register_new_ioapic_gsi0()
Change-Id: I6b0e4021595fb160ae3bf798468f4505b460266f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/i82801dx')
| -rw-r--r-- | src/southbridge/intel/i82801dx/lpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 1de3766563..1569c1c14b 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -50,7 +50,7 @@ static void i82801dx_enable_ioapic(struct device *dev) pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - setup_ioapic(VIO_APIC_VADDR, 0x02); + register_new_ioapic_gsi0(VIO_APIC_VADDR); ioapic_set_boot_config(VIO_APIC_VADDR, true); } |