diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-23 16:32:20 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-25 17:44:11 +0000 |
| commit | 972d9f2cce2792b847c4c1879f5b52c19585c37c (patch) | |
| tree | 87166acd957448e6b262a331106e7a276806043c /src/southbridge/intel/i82801dx | |
| parent | 887d4ed912ef80afbf7827150f52e207edc9c033 (diff) | |
arch/x86: consolidate HPET base address definitions
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and
the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO
region which is 0xfed00000 on all chipsets and SoCs in the coreboot
tree. Since these two different constants are used in different places
that however might end up used in the same coreboot build, drop the
Kconfig option and use the definition from arch/x86 instead. Since it's
no longer needed to check for a mismatch of those two constants, the
corresponding checks are dropped too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801dx')
| -rw-r--r-- | src/southbridge/intel/i82801dx/lpc.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 972ca76462..238661cd2d 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/hpet.h> #include <arch/io.h> #include <arch/ioapic.h> #include <console/console.h> @@ -213,7 +214,7 @@ static void enable_hpet(struct device *dev) u32 reg32, hpet, val; /* Set HPET base address and enable it */ - printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", CONFIG_HPET_ADDRESS); + printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", HPET_BASE_ADDRESS); reg32 = pci_read_config32(dev, GEN_CNTL); /* * Bit 17 is HPET enable bit. @@ -221,7 +222,7 @@ static void enable_hpet(struct device *dev) */ reg32 &= ~(3 << 15); /* Clear it */ - hpet = CONFIG_HPET_ADDRESS >> 12; + hpet = HPET_BASE_ADDRESS >> 12; hpet &= 0x3; reg32 |= (hpet << 15); @@ -234,7 +235,7 @@ static void enable_hpet(struct device *dev) val &= 0x7; if ((val & 0x4) && (hpet == (val & 0x3))) { - printk(BIOS_INFO, "HPET enabled at 0x%x\n", CONFIG_HPET_ADDRESS); + printk(BIOS_INFO, "HPET enabled at 0x%x\n", HPET_BASE_ADDRESS); } else { printk(BIOS_WARNING, "HPET was not enabled correctly\n"); reg32 &= ~(1 << 17); /* Clear Enable */ |