diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-04-17 15:20:40 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-29 01:20:54 +0000 |
| commit | 240baa31e8a804029069e21f523556d8628f6001 (patch) | |
| tree | 1d58b857233bb5029da1ac99e11c86d911618a25 /src/southbridge/intel/i82371eb/fadt.c | |
| parent | 097f5404607ea548cc49feb82bd99663c1ada0fe (diff) | |
ACPI: Make FADT entries for RTC/CMOS architectural
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY
that points to same offset. Since the century field inside
RTC falls within the NVRAM space, and could interfere with
OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY.
There were no reference for the use of offset 0x48 for century.
Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel/i82371eb/fadt.c')
| -rw-r--r-- | src/southbridge/intel/i82371eb/fadt.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 00e204ebef..43e119b746 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -31,8 +31,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ - fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */ - fadt->mon_alrm = 0x0; /* not supported */ + /* * bit meaning * 0 1: We have user-visible legacy devices |