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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-11-24 16:32:05 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-30 08:13:33 +0000 |
| commit | 3aa17f76044f92dd772cd2833fa8f30031e17f35 (patch) | |
| tree | eb2c3d6fcdfb7dd67d0678c688fc904030f54015 /src/southbridge/intel/i82371eb/acpi/isabridge.asl | |
| parent | 2fa1cb15de4b03155277ae96c389753690a5e517 (diff) | |
AGESA,binaryPI: Fix stack location on entry to romstage
For BSP CPU, set up stack location to match the symbol from car.ld.
For AP CPUs the stack is located outside _car_region and is currently
not accounted for in the linker scripts.
Change-Id: I0ec84ae4e73ecca5034f799cdc2a5c1056ad8b74
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82371eb/acpi/isabridge.asl')
0 files changed, 0 insertions, 0 deletions