diff options
| author | Tristan Corrick <tristan@corrick.kiwi> | 2018-11-30 22:53:50 +1300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-03 13:14:06 +0000 |
| commit | 63626b1a4a31588995ff6f0ba42952b6086cbded (patch) | |
| tree | 968555763c26df36af3e64b7322b3c68d6c19913 /src/southbridge/intel/common/pmutil.h | |
| parent | 32ceed8f269e48d9d500ee2ec9ba5b3f4435285e (diff) | |
sb/intel/common: Create a common PCH finalise implementation
The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak.
Lynx Point now benefits from being able to write-protect the flash chip.
For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done
in bd82x6x.
Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is
configured, flashrom reports all flash regions as read-only, and does
not manage to alter the contents of the flash chip.
Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to
work as before.
Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/common/pmutil.h')
| -rw-r--r-- | src/southbridge/intel/common/pmutil.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 2e761ccef2..47813f7d02 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -20,10 +20,20 @@ #include <cpu/x86/smm.h> #define D31F0_PMBASE 0x40 +#define D31F0_GEN_PMCON_1 0xa0 +#define SMI_LOCK (1 << 4) +#define D31F0_GEN_PMCON_2 0xa2 #define D31F0_GEN_PMCON_3 0xa4 #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) #define SLEEP_AFTER_POWER_FAIL (1 << 0) +#define D31F0_GEN_PMCON_LOCK 0xa6 +#define ACPI_BASE_LOCK (1 << 1) +#define SLP_STR_POL_LOCK (1 << 2) +#define D31F0_ETR3 0xac +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20) +#define ETR3_CF9LOCK (1 << 31) #define D31F0_GPIO_ROUT 0xb8 #define GPI_DISABLE 0x00 #define GPI_IS_SMI 0x01 |