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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-01-05 15:39:16 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-05-09 18:08:45 +0000 |
| commit | 83faa5d804d183a26b0fa66b5d55bbe5f3b72c89 (patch) | |
| tree | 9818e9b83a6e24884516182f20380850039bef86 /src/southbridge/intel/common/pmbase.c | |
| parent | 923b8ec18085d9b03162a1aae8dfd3aeff2d4fa0 (diff) | |
mb/google,intel: Use common ChromeEC code for lid shutdown
Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74514
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/southbridge/intel/common/pmbase.c')
| -rw-r--r-- | src/southbridge/intel/common/pmbase.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 872d994210..5a339c91f7 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -7,6 +7,7 @@ #include <bootmode.h> #include <device/pci_ops.h> #include <device/pci_type.h> +#include <halt.h> #include <stdint.h> #include "pmbase.h" @@ -94,6 +95,16 @@ int platform_is_resuming(void) return acpi_get_sleep_type() == ACPI_S3; } +void poweroff(void) +{ + uint32_t pm1_cnt; + + /* Go to S5 */ + pm1_cnt = read_pmbase32(PM1_CNT); + pm1_cnt |= (0xf << 10); + write_pmbase32(PM1_CNT, pm1_cnt); +} + #define ACPI_SCI_IRQ 9 void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) |