diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-09-05 18:34:30 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-13 17:25:02 +0000 |
| commit | 7673f2f5e9dab30c655d2d76d76394dd750459a6 (patch) | |
| tree | 617e53a71f21ea8a32971a2ce44c10ba43107a69 /src/southbridge/intel/common/pciehp.c | |
| parent | e14d7def4f2b77e676ca8997a4e1505998b7d53d (diff) | |
soc/intel/cannonlake: Add ramstage uart debug support
Use fixed resources for LPSS uart devices for debugging purpose.
BUG=NONE
BRANCH=NONE
TEST=Boot up with coreboot rom, without this changes, serial log will
stop print anything during PCI resourcre setup as MMIO address of UART
will be re-assigned.
Change-Id: Ib773e01d5f5358f13297400075d6920793200b88
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/common/pciehp.c')
0 files changed, 0 insertions, 0 deletions