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authorPatrick Georgi <pgeorgi@google.com>2020-05-10 16:41:01 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-11 17:11:40 +0000
commit6b5bc77c9b22c398262ff3f4dae3e14904c57366 (patch)
treeab40c703d92f906f8604635f091f809b59233efa /src/southbridge/intel/common/acpi
parenta83c6bc907b8ef77935ba62789bc4ed60716986d (diff)
treewide: Remove "this file is part of" lines
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/common/acpi')
-rw-r--r--src/southbridge/intel/common/acpi/pcie.asl1
-rw-r--r--src/southbridge/intel/common/acpi/pcie_port.asl1
-rw-r--r--src/southbridge/intel/common/acpi/platform.asl1
-rw-r--r--src/southbridge/intel/common/acpi/sleepstates.asl1
-rw-r--r--src/southbridge/intel/common/acpi/smbus.asl1
5 files changed, 0 insertions, 5 deletions
diff --git a/src/southbridge/intel/common/acpi/pcie.asl b/src/southbridge/intel/common/acpi/pcie.asl
index a3076f988e..8f496d38d8 100644
--- a/src/southbridge/intel/common/acpi/pcie.asl
+++ b/src/southbridge/intel/common/acpi/pcie.asl
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
/* Intel 6/7 Series PCH PCIe support */
diff --git a/src/southbridge/intel/common/acpi/pcie_port.asl b/src/southbridge/intel/common/acpi/pcie_port.asl
index 34ab79b78c..988c8170e9 100644
--- a/src/southbridge/intel/common/acpi/pcie_port.asl
+++ b/src/southbridge/intel/common/acpi/pcie_port.asl
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
/* Included in each PCIe Root Port device */
diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl
index 7451e44260..b92872920c 100644
--- a/src/southbridge/intel/common/acpi/platform.asl
+++ b/src/southbridge/intel/common/acpi/platform.asl
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
/* The APM port can be used for generating software SMIs */
diff --git a/src/southbridge/intel/common/acpi/sleepstates.asl b/src/southbridge/intel/common/acpi/sleepstates.asl
index ed8b1b8945..eae7642d2b 100644
--- a/src/southbridge/intel/common/acpi/sleepstates.asl
+++ b/src/southbridge/intel/common/acpi/sleepstates.asl
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
Name(\_S0, Package(){0x0,0x0,0x0,0x0})
#if !CONFIG(HAVE_ACPI_RESUME)
diff --git a/src/southbridge/intel/common/acpi/smbus.asl b/src/southbridge/intel/common/acpi/smbus.asl
index 9fc516fe54..83c8991fbf 100644
--- a/src/southbridge/intel/common/acpi/smbus.asl
+++ b/src/southbridge/intel/common/acpi/smbus.asl
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
// Intel SMBus Controller 0:1f.3