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authorPatrick Rudolph <patrick.rudolph@9elements.com>2023-10-02 08:55:52 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-10-12 12:39:42 +0000
commit2fcef78ff84c184f7a9dd0e007c95b56cda552f5 (patch)
tree8d70116da99863027a0df44d707202bb820314b7 /src/southbridge/intel/bd82x6x
parentf94a522086acb7ce2d4b9483953f73caad5c38d8 (diff)
sb/intel/bd82x6x: Warn about slow PCIe downstream devices
Warn when a device took longer than usual to appear. Use the PDS bit to detect if a root port has a downstream device connected and warn if enumeration failed. Test: On Lenovo X220 all PCIe device are visible, thus the added code path is never taken. Change-Id: I86b498b89d672b239d9951e116dc3680030666a6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78229 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/pcie.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 2658fd31ef..45ce5aadd3 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -243,12 +243,18 @@ static void pch_pcie_enable(struct device *dev)
static void pch_pciexp_scan_bridge(struct device *dev)
{
+ uint32_t cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
+
if (CONFIG(PCIEXP_HOTPLUG) && pci_is_hotplugable(dev)) {
pciexp_hotplug_scan_bridge(dev);
} else {
/* Normal PCIe Scan */
pciexp_scan_bridge(dev);
}
+ if ((pci_read_config16(dev, cap + PCI_EXP_SLTSTA) & PCI_EXP_SLTSTA_PDS) &&
+ !dev_is_active_bridge(dev))
+ printk(BIOS_WARNING, "%s: Has a slow downstream device. Enumeration failed.\n",
+ dev_path(dev));
/* Late Power Management init after bridge device enumeration */
pch_pcie_pm_late(dev);