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authorJames Ye <jye836@gmail.com>2020-02-22 20:30:49 +1100
committerNico Huber <nico.h@gmx.de>2021-02-06 12:33:32 +0000
commita85d4a5a9c23ac891e2587733088154efeaad6b3 (patch)
tree6d18db87f7ed8296b12f4f4152de4735385cfbea /src/southbridge/intel/bd82x6x
parent841491c06fb1dc1435fc27c3097136e4b54f60c6 (diff)
sb/intel/{bd82x6x,ibexpeak}: hide MEI if ME inoperable
- Add Kconfig option to hide the Management Engine Interface device so the OS doesn't try to access it, if the Management Engine is in an inoperable mode, e.g. if me_cleaner is used. - Also hide the MEI if the ME is in Soft Temp Disable mode. Change-Id: Ie4a35bf5fc196e0a02b7591cdb8633d38f0c7f3e Signed-off-by: James Ye <jye836@gmail.com> Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39074 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig8
-rw-r--r--src/southbridge/intel/bd82x6x/me.c7
-rw-r--r--src/southbridge/intel/bd82x6x/me_8.x.c7
3 files changed, 20 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 21816e5136..e3ad885cb4 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -56,4 +56,12 @@ config HPET_MIN_TICKS
hex
default 0x80
+config HIDE_MEI_ON_ERROR
+ bool "Hide MEI device on error"
+ default n
+ help
+ If you enable this option, the Management Engine Interface
+ device will be hidden when ME is in an inoperable mode, e.g.
+ if me_cleaner was used.
+
endif
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 2adfbd5c98..fe2a37c849 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -254,6 +254,10 @@ static void intel_me_init(struct device *dev)
switch (path) {
case ME_S3WAKE_BIOS_PATH:
+ case ME_DISABLE_BIOS_PATH:
+#if CONFIG(HIDE_MEI_ON_ERROR)
+ case ME_ERROR_BIOS_PATH:
+#endif
intel_me_hide(dev);
break;
@@ -279,9 +283,10 @@ static void intel_me_init(struct device *dev)
*/
break;
+#if !CONFIG(HIDE_MEI_ON_ERROR)
case ME_ERROR_BIOS_PATH:
+#endif
case ME_RECOVERY_BIOS_PATH:
- case ME_DISABLE_BIOS_PATH:
case ME_FIRMWARE_UPDATE_BIOS_PATH:
break;
}
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index b0226a6e9a..f5a39ecfa6 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -242,6 +242,10 @@ static void intel_me_init(struct device *dev)
switch (path) {
case ME_S3WAKE_BIOS_PATH:
+ case ME_DISABLE_BIOS_PATH:
+#if CONFIG(HIDE_MEI_ON_ERROR)
+ case ME_ERROR_BIOS_PATH:
+#endif
intel_me_hide(dev);
break;
@@ -268,9 +272,10 @@ static void intel_me_init(struct device *dev)
*/
break;
+#if !CONFIG(HIDE_MEI_ON_ERROR)
case ME_ERROR_BIOS_PATH:
+#endif
case ME_RECOVERY_BIOS_PATH:
- case ME_DISABLE_BIOS_PATH:
case ME_FIRMWARE_UPDATE_BIOS_PATH:
break;
}