diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-29 09:14:46 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-29 01:23:10 +0200 |
| commit | a014521b9021f5876594e8be038dfd93a24702eb (patch) | |
| tree | 34848143756b6ffdc6314b393c2b09576dbccf18 /src/southbridge/intel/bd82x6x | |
| parent | 7686a56574a6773717b49a51786f301970d1c69c (diff) | |
sandy/ivybridge: Native raminit (lint clean)
Remove some trailing whitespaces and add header guards for code
introduced in:
7686a56 sandy/ivybridge: Native raminit
Change-Id: Ifc9a785ea3a43cfe1f406b57eeba9b5f94f36711
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6393
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_me_native.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_me_native.c b/src/southbridge/intel/bd82x6x/early_me_native.c index ab54ffd61c..f327aec8c5 100644 --- a/src/southbridge/intel/bd82x6x/early_me_native.c +++ b/src/southbridge/intel/bd82x6x/early_me_native.c @@ -138,7 +138,7 @@ int intel_early_me_init_done(u8 status) u32 meDID; hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xff000) >> 12; - + opmode = (hfs & 0xf0) >> 4; errorcode = hfs & 0xf; @@ -167,7 +167,7 @@ int intel_early_me_init_done(u8 status) printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16); printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24); printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28); - + // Poll cpu replaced for 50ms millisec = 0; while ((((me_fws2 & 0x100) >> 8) == 0) && millisec < 50) { @@ -178,7 +178,7 @@ int intel_early_me_init_done(u8 status) if (millisec >= 50 || ((me_fws2 & 0x100) >> 8) == 0x0) { printk(BIOS_NOTICE, "Waited long enough, or CPU was not replaced, continue...\n"); } else if ((me_fws2 & 0x100) == 0x100) { - if ((me_fws2 & 0x80) == 0x80) { + if ((me_fws2 & 0x80) == 0x80) { printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n"); reg16 = pcie_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80; pcie_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16); @@ -230,7 +230,7 @@ int intel_early_me_init_done(u8 status) printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24); printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28); - + /* Return the requested BIOS action */ printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n", me_ack_values[(hfs & 0xe) >> 1]); |