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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-08-13 09:37:42 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-12 04:21:59 +0100 |
| commit | 04c5bae39054aedbff1865d9dd2633260c23ece3 (patch) | |
| tree | 21eb979f2c2341143be67decbcd25443108b6c27 /src/southbridge/intel/bd82x6x/smbus.c | |
| parent | 2c485180a8613695b4886299efca4276fd17be31 (diff) | |
Define post codes for OS boot and resume
And move the pre-hardwaremain post code to 0x79
so it comes before hardwaremain at 0x80.
Emit these codes from ACPI OS resume vector as well
as the finalize step in bd82x6x southbridge.
Change-Id: I7f258998a2f6549016e99b67bc21f7c59d2bcf9e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1702
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/smbus.c')
0 files changed, 0 insertions, 0 deletions