No warnings day, next round.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 7 insertions, 17 deletions

diff --git a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
index 0e34c31c1e..5490777d42 100644
--- a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
+++ b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
@@ -35,7 +35,7 @@ static void enable_cf9(void)
 	enable_cf9_x(sbbusn, sbdn);
 }
 
-static void hard_reset(void)
+void hard_reset(void)
 {
         set_bios_reset();
         /* reset */
@@ -68,7 +68,7 @@ static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
 
 }
 
-static void soft_reset(void)
+void soft_reset(void)
 {
 
 	unsigned sblk = get_sblk();
diff --git a/src/southbridge/amd/cs5536/cs5536_ide.c b/src/southbridge/amd/cs5536/cs5536_ide.c
index 4acf3ed61a..c4cc652e93 100644
--- a/src/southbridge/amd/cs5536/cs5536_ide.c
+++ b/src/southbridge/amd/cs5536/cs5536_ide.c
@@ -46,13 +46,6 @@ static void ide_init(struct device *dev)
 	pci_write_config32(dev, IDE_CFG, ide_cfg);
 }
 
-static void ide_enable(struct device *dev)
-{
-
-	printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__);
-
-}
-
 static struct device_operations ide_ops = {
 	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,
diff --git a/src/southbridge/amd/rs780/rs780_early_setup.c b/src/southbridge/amd/rs780/rs780_early_setup.c
index 72ac730cb0..2ebda9a7da 100644
--- a/src/southbridge/amd/rs780/rs780_early_setup.c
+++ b/src/southbridge/amd/rs780/rs780_early_setup.c
@@ -371,10 +371,9 @@ static void k8_optimization(void)
 #endif	/* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */
 
 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1		/* save some spaces */
-void fam10_optimization(void)
+static void fam10_optimization(void)
 {
 	device_t cpu_f0, cpu_f2, cpu_f3;
-	msr_t msr;
 	u32 val;
 
 	printk(BIOS_INFO, "fam10_optimization()\n");
@@ -634,16 +633,16 @@ static void rs780_por_init(device_t nb_dev)
 }
 
 /* enable CFG access to Dev8, which is the SB P2P Bridge */
-static void enable_rs780_dev8()
+static void enable_rs780_dev8(void)
 {
 	set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
 }
 
-static void rs780_before_pci_init()
+static void rs780_before_pci_init(void)
 {
 }
 
-static void rs780_early_setup()
+static void rs780_early_setup(void)
 {
 	device_t nb_dev = PCI_DEV(0, 0, 0);
 	printk(BIOS_INFO, "rs780_early_setup()\n");
diff --git a/src/southbridge/amd/sb700/sb700_smbus.c b/src/southbridge/amd/sb700/sb700_smbus.c
index 7ba2a7d264..ec3f94c7bc 100644
--- a/src/southbridge/amd/sb700/sb700_smbus.c
+++ b/src/southbridge/amd/sb700/sb700_smbus.c
@@ -205,7 +205,7 @@ static void alink_ab_indx(u32 reg_space, u32 reg_addr,
 /* space = 0: AX_INDXC, AX_DATAC
  * space = 1: AX_INDXP, AX_DATAP
  */
-static void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
+static inline void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
 			  u32 mask, u32 val)
 {
 	u32 tmp;
diff --git a/src/southbridge/amd/sb700/sb700_smbus.h b/src/southbridge/amd/sb700/sb700_smbus.h
index 07166a5b52..6acfa99090 100644
--- a/src/southbridge/amd/sb700/sb700_smbus.h
+++ b/src/southbridge/amd/sb700/sb700_smbus.h
@@ -20,8 +20,6 @@
 #ifndef SB700_SMBUS_H
 #define SB700_SMBUS_H
 
-//#include <stdint.h>
-
 #define SMBHSTSTAT 0x0
 #define SMBSLVSTAT 0x1
 #define SMBHSTCTRL 0x2