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authorDuncan Laurie <dlaurie@chromium.org>2016-09-19 17:24:55 -0700
committerDuncan Laurie <dlaurie@chromium.org>2016-09-19 19:05:10 -0700
commit24de342438208d9b843e87627f15b9a272285b0f (patch)
treec4d1c45c2d8cddf68b478e5a739f1b5a313486a2 /src/southbridge/amd/rs690
parenta5e419c51187d24818f056327746a18676fe3a20 (diff)
mainboard/google/reef: Enable cr50 TPM interrupt
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during verstage. The interrupt is left in APIC mode as the GPE is still latched when the GPIO is pulled low. BUG=chrome-os-partner:53336 Change-Id: I28ade5ee3bf08fa17d8cabf16287319480f03921 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/southbridge/amd/rs690')
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