diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2023-10-26 13:25:35 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-11-02 17:25:32 +0000 |
| commit | ebd4c3d11304e5ce8e8ff7da57570da19a8bf028 (patch) | |
| tree | fa5af77bafbb974a1dbdc3deabfd43aafcd725fa /src/soc | |
| parent | f89bb8283232dbb43d20fba5aa9d8c5c0f153822 (diff) | |
Revert "soc/intel/{tigerlake,meteorlake}: Check ITBT FW version"
This reverts commit 2e10a6d6f3ec46bcaf75bd066319d51f001be764.
Reason for revert: The FW version check is not supported except
for ADL platform. Reverted change broke S0ix functionality;
the original CL was added as HW W/A for ADL ONLY.
BUG=b:306214725
TEST=S0ix cycles on Rex with TBT Device attached.
Change-Id: Ib8eb11d36eac4e1c94a3349386442fa3eeeaef37
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78457
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/meteorlake/acpi/tcss.asl | 8 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/acpi/tcss_dma.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss.asl | 8 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss_dma.asl | 3 |
4 files changed, 2 insertions, 20 deletions
diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index fd68744579..84e15fd128 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -452,10 +452,6 @@ Scope (\_SB.PCI0) /* DMA0 is not in D3Cold now. */ \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ - If (\_SB.PCI0.TDM0.IF30 != 1) { - Return - } - Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { /* Put RP0 to D3 cold. */ @@ -511,10 +507,6 @@ Scope (\_SB.PCI0) /* DMA1 is not in D3Cold now */ \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */ - If (\_SB.PCI0.TDM1.IF30 != 1) { - Return - } - Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { /* Put RP2 to D3 cold. */ diff --git a/src/soc/intel/meteorlake/acpi/tcss_dma.asl b/src/soc/intel/meteorlake/acpi/tcss_dma.asl index 2586ecbbc7..90824698bb 100644 --- a/src/soc/intel/meteorlake/acpi/tcss_dma.asl +++ b/src/soc/intel/meteorlake/acpi/tcss_dma.asl @@ -11,8 +11,7 @@ Field (DPME, AnyAcc, NoLock, Preserve) , 6, PMES, 1, /* 15, PME_STATUS */ Offset(0xC8), /* 0xC8, TBT NVM FW Revision */ - , 30, - IF30, 1, /* ITBT FW Version Bit30 */ + , 31, INFR, 1, /* TBT NVM FW Ready */ Offset(0xEC), /* 0xEC, TBT TO PCIE Register */ TB2P, 32, /* TBT to PCIe */ diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 2ae7049ee1..5af78edb8a 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -567,10 +567,6 @@ Scope (\_SB.PCI0) /* DMA0 is not in D3Cold now. */ \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ - If (\_SB.PCI0.TDM0.IF30 != 1) { - Return - } - Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { /* Put RP0 to D3 cold. */ @@ -626,10 +622,6 @@ Scope (\_SB.PCI0) /* DMA1 is not in D3Cold now */ \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */ - If (\_SB.PCI0.TDM1.IF30 != 1) { - Return - } - Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { /* Put RP2 to D3 cold. */ diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index 951d83d2e3..90824698bb 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -11,8 +11,7 @@ Field (DPME, AnyAcc, NoLock, Preserve) , 6, PMES, 1, /* 15, PME_STATUS */ Offset(0xC8), /* 0xC8, TBT NVM FW Revision */ - , 30, - IF30, 1, /* ITBT FW Version Bit30 */ + , 31, INFR, 1, /* TBT NVM FW Ready */ Offset(0xEC), /* 0xEC, TBT TO PCIE Register */ TB2P, 32, /* TBT to PCIe */ |