summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2021-06-15 16:01:44 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-06-16 16:37:57 +0000
commit1532d1c4073107370ddd4a3c4db6945c54bfb330 (patch)
treeba12817085c46f25a4f2e58e8c6801dc4f2e5b6c /src/soc
parent17c89018a5084cad8ddc4e828b5fbb85f35c91ef (diff)
soc/amd/cezanne,picasso: add AOAC offset define for the eMMC controller
BUG=b:184978118 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I03554a151aa6a6d9e15d74c63cd02239b788808a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/cezanne/include/soc/southbridge.h1
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index e82f33f9c8..f90964bd47 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -117,6 +117,7 @@
#define FCH_AOAC_DEV_UART1 12
#define FCH_AOAC_DEV_AMBA 17
#define FCH_AOAC_DEV_ESPI 27
+#define FCH_AOAC_DEV_EMMC 28
void fch_pre_init(void);
void fch_early_init(void);
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index b623ed382e..e9d891ca15 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -130,6 +130,7 @@
#define FCH_AOAC_DEV_AMBA 17
#define FCH_AOAC_DEV_UART3 26
#define FCH_AOAC_DEV_ESPI 27
+#define FCH_AOAC_DEV_EMMC 28
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */