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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2021-08-31 21:14:52 +0530
committerFelix Held <felix-coreboot@felixheld.de>2021-09-05 19:26:06 +0000
commitfe2ac34d956d9370949336e31d8a21576114deaa (patch)
tree0770a21f7a32ea3342fb83b04ad0f6b42dc197b4 /src/soc
parent024b2bd2edf738b3f3a527e27deb5186b50cf2ca (diff)
soc/intel/common: Add PMC IPC commands for FIVR
Add PMC IPC commands information for FIVR control functionality. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/pmc_ipc.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h
index b67abc0fcd..fb33a075ee 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h
@@ -16,6 +16,15 @@
#define PMC_IPC_CMD_SIZE_SHIFT 16
#define PMC_IPC_CMD_SIZE_MASK 0xff
+/* IPC command to control FIVR Configuration */
+#define PMC_IPC_CMD_COMMAND_FIVR 0xA3
+/* IPC subcommand to write FIVR Register */
+#define PMC_IPC_CMD_CMD_ID_FIVR_WRITE 0x01
+/* IPC subcommand to control RFI Control 0 register logic write */
+#define PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC 0x00
+/* IPC subcommand to control RFI Control 4 register logic write */
+#define PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC 0x01
+
#define PMC_IPC_CMD_FIELD(name, val) \
((((val) & PMC_IPC_CMD_##name##_MASK) << PMC_IPC_CMD_##name##_SHIFT))