diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-03-11 19:37:32 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-03-12 20:31:55 +0000 |
| commit | e77d939321e79ae04a1ebc8142b9d5949c6fd4d1 (patch) | |
| tree | 180a855e3ffe3d187de5e116194e4c06dda67cef /src/soc | |
| parent | 8494d8a1653658e05cf86c6c1d50cbb9039c1c52 (diff) | |
soc/amd/cezanne: add XHCI SCI/GEVENT setup
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32fd9b7165306266613e8497b5d07473b5fea02d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/xhci.c | 52 |
2 files changed, 53 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index aa82c99ba4..f099ad81d8 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -35,6 +35,7 @@ ramstage-y += pcie_gpp.c ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c +ramstage-y += xhci.c smm-y += gpio.c smm-y += smihandler.c diff --git a/src/soc/amd/cezanne/xhci.c b/src/soc/amd/cezanne/xhci.c new file mode 100644 index 0000000000..a77830c7b0 --- /dev/null +++ b/src/soc/amd/cezanne/xhci.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/gpio_banks.h> +#include <amdblocks/smi.h> +#include <bootstate.h> +#include <device/device.h> +#include <drivers/usb/pci_xhci/pci_xhci.h> +#include <soc/pci_devs.h> +#include <soc/smi.h> + +static const struct sci_source xhci_sci_sources[] = { + { + .scimap = SMITYPE_XHC0_PME, + .gpe = GEVENT_31, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC1_PME, + .gpe = GEVENT_31, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + } +}; + +enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) +{ + if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + return CB_ERR_ARG; + + if (dev->bus->dev->path.pci.devfn != PCIE_ABC_A_DEVFN) + return CB_ERR_ARG; + + if (dev->path.type != DEVICE_PATH_PCI) + return CB_ERR_ARG; + + if (dev->path.pci.devfn == XHCI0_DEVFN) + *gpe = xhci_sci_sources[0].gpe; + else if (dev->path.pci.devfn == XHCI1_DEVFN) + *gpe = xhci_sci_sources[1].gpe; + else + return CB_ERR_ARG; + + return CB_SUCCESS; +} + +static void configure_xhci_sci(void *unused) +{ + gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources)); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL); |