diff options
| author | Furquan Shaikh <furquan@google.com> | 2021-03-08 16:21:07 -0800 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-03-13 13:26:39 +0000 |
| commit | d09d8de7da5acd86c0018b2f11046b388c72e226 (patch) | |
| tree | 87286a11c0b7d64a52fa4b32445ebe8a7e7d752f /src/soc | |
| parent | de85f5ce2a23552ff53959782f907062858a623f (diff) | |
soc/intel/common/fast_spi: Fix check-fmap-16mib-crossing check
Currently, `check-fmap-16mib-crossing` compares the offset and end of
each SPI flash region to 16MiB to ensure that no region is placed
across this 16MiB boundary from the start of SPI flash. What really
needs to be checked is that the region isn't placed across the 16MiB
boundary from the end of BIOS region. Thus, current check works only
if the SPI flash is 32MiB under the assumption that the BIOS region
is mapped at the top of SPI flash. However, this check will not work
if a flash part greater than 32MiB is used.
This change replaces the hardcoded boundary value of 16MiB with a
value calculated by subtracting 16MiB from the SPI flash size (if it
is greater than 16MiB). This calculated value is used as the boundary
that no region defined in the flashmap should be placed across.
The assumption here is that BIOS region is always placed at the top of
SPI flash. Hence, the standard decode window would be from
end_of_flash - 16M to end_of_flash (because end_of_flash =
end_of_bios_region). Currently, there is no consistency in the name
used for BIOS region in flashmap layout for boards in
coreboot. But all Intel-based boards (except APL and GLK) place BIOS
region at the end of SPI flash. Since APL and GLK do not support the
extended window, this check does not matter for these platforms.
Change-Id: Icff83e5bffacfd443c1c3fbc101675c4a6f75e24
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51359
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/Makefile.inc | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/src/soc/intel/common/block/fast_spi/Makefile.inc b/src/soc/intel/common/block/fast_spi/Makefile.inc index eeaae51d75..4fe6163773 100644 --- a/src/soc/intel/common/block/fast_spi/Makefile.inc +++ b/src/soc/intel/common/block/fast_spi/Makefile.inc @@ -32,22 +32,34 @@ postcar-y += mmap_boot.c ramstage-y += mmap_boot.c smm-y += mmap_boot.c -# Check to ensure that no sections in the FMAP cross 16MiB boundary if -# the platform supports split decode windows for BIOS region greater -# than 16MiB. +# When using extended BIOS window, no sub-region within the BIOS region must +# cross 16MiB boundary from the end of the BIOS region. This is because the +# top 16MiB of the BIOS region are decoded by the standard window from +# (4G - 16M) to 4G. There is no standard section name that identifies the BIOS +# region in flashmap. This check assumes that BIOS region is placed at the top +# of SPI flash and hence calculates the boundary as flash_size - 16M. If any +# region within the SPI flash crosses this boundary, then the check complains +# and exits. $(call add_intermediate, check-fmap-16mib-crossing) check-fmap-16mib-crossing: $(obj)/fmap_config.h fmap_get() { awk "/$$1/ { print \$$NF }" < $<; }; \ \ flash_offset=$$(fmap_get FMAP_SECTION_FLASH_START); \ + flash_size=$$(fmap_get FMAP_SECTION_FLASH_SIZE); \ + if [ $$((flash_size)) -le $$((0x1000000)) ]; then \ + exit; \ + fi; \ + bios_16M_boundary=$$((flash_size-0x1000000)); \ for x in $$(grep "FMAP_TERMINAL_SECTIONS" < $< | cut -d\" -f2); \ do \ start=$$(fmap_get "FMAP_SECTION_$${x}_START"); \ size=$$(fmap_get "FMAP_SECTION_$${x}_SIZE"); \ start=$$((start-flash_offset)); \ end=$$((start+size-1)); \ - if [ $$start -lt 16777216 ] && [ $$end -ge 16777216 ]; then \ + if [ $$((start)) -lt $$((bios_16M_boundary)) ] && \ + [ $$((end)) -ge $$((bios_16M_boundary)) ]; \ + then \ echo "ERROR: $$x crosses 16MiB boundary"; \ fail=1; \ break; \ |