diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-08-30 10:33:50 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-03 00:12:37 +0000 |
| commit | b4d3a1436070e9388caed6fd0756b5009219f31d (patch) | |
| tree | 55b09e0c18f991acb3f6736ad43d1d34240135ea /src/soc | |
| parent | 8f4098bb3dfa069ae330257c7cd677806634ea4a (diff) | |
skylake: Default to `BOARD_TYPE_DESKTOP` for PCH-H
Set the `UserBd` FSP-M UPD to `BOARD_TYPE_DESKTOP` by default on PCH-H.
Remove now-redundant mainboard code to set the `UserBd` UPD.
Change-Id: I349abe5d89f562c158ce9baadbca2b2f56695846
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57261
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/romstage/fsp_params.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index 21526e4848..7af0a6eff2 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -82,7 +82,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->ProbelessTrace = 0; m_cfg->SaGv = config->SaGv; - m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + if (CONFIG(SKYLAKE_SOC_PCH_H)) + m_cfg->UserBd = BOARD_TYPE_DESKTOP; + else + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->RMT; m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = 0; |