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authorJarried Lin <jarried.lin@mediatek.corp-partner.google.com>2024-07-16 18:26:23 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-07-22 14:07:34 +0000
commita87649cee3883fd0044a212500487acd12912297 (patch)
tree1e2bd5c8b3aeb50aefd6269577184b4a755737c4 /src/soc
parentae37d6158efdae7f902ba058628b2115daee0b88 (diff)
soc/mediatek: Move memmory macros into MediaTek common directory
To reduce duplicate memmory macros of MediaTek SoCs, move the header file to a common directory. TEST=Build geralt pass BUG=b:317009620 Change-Id: Iea4add8fe3735085c13438a2e177bec177913191 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83571 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/mediatek/common/include/soc/memlayout.h22
-rw-r--r--src/soc/mediatek/mt8173/memlayout.ld17
-rw-r--r--src/soc/mediatek/mt8183/memlayout.ld19
-rw-r--r--src/soc/mediatek/mt8186/include/soc/memlayout.ld19
-rw-r--r--src/soc/mediatek/mt8188/include/soc/memlayout.ld17
-rw-r--r--src/soc/mediatek/mt8195/include/soc/memlayout.ld22
6 files changed, 28 insertions, 88 deletions
diff --git a/src/soc/mediatek/common/include/soc/memlayout.h b/src/soc/mediatek/common/include/soc/memlayout.h
new file mode 100644
index 0000000000..f51c2a1996
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/memlayout.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+/*
+ * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
+ * It will be returned before starting the ramstage.
+ * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
+ */
+#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
+#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
+#define DRAM_INIT_CODE(addr, size) \
+ REGION(dram_init_code, addr, size, 64K)
+
+#define DRAM_DMA(addr, size) \
+ REGION(dram_dma, addr, size, 4K) \
+ _ = ASSERT(size % 4K == 0, \
+ "DRAM DMA buffer should be multiple of smallest page size (4K)!");
+
+#define EARLY_INIT(addr, size) \
+ REGION(early_init_data, addr, size, 4)
diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld
index 224dbdabaa..c593853c3c 100644
--- a/src/soc/mediatek/mt8173/memlayout.ld
+++ b/src/soc/mediatek/mt8173/memlayout.ld
@@ -1,21 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/*
- * SRAM_L2C is the half part of L2 cache that we borrow it to be used as SRAM.
- * It will be returned before starting the ramstage.
- * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
- */
-#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
-#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
-
-#define DRAM_DMA(addr, size) \
- REGION(dram_dma, addr, size, 4K) \
- _ = ASSERT(size % 4K == 0, \
- "DRAM DMA buffer should be multiple of smallest page size (4K)!");
+#include <soc/memlayout.h>
SECTIONS
{
diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld
index c5d9d08324..b1b9027798 100644
--- a/src/soc/mediatek/mt8183/memlayout.ld
+++ b/src/soc/mediatek/mt8183/memlayout.ld
@@ -1,23 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/*
- * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
- * It will be returned before starting the ramstage.
- * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
- */
-#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
-#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
-#define DRAM_INIT_CODE(addr, size) \
- REGION(dram_init_code, addr, size, 4)
-
-#define DRAM_DMA(addr, size) \
- REGION(dram_dma, addr, size, 4K) \
- _ = ASSERT(size % 4K == 0, \
- "DRAM DMA buffer should be multiple of smallest page size (4K)!");
+#include <soc/memlayout.h>
SECTIONS
{
diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
index f927b608a8..a47e7c5ae4 100644
--- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
@@ -1,23 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/*
- * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
- * It will be returned before starting the ramstage.
- * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
- */
-#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
-#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
-#define DRAM_INIT_CODE(addr, size) \
- REGION(dram_init_code, addr, size, 64K)
-
-#define DRAM_DMA(addr, size) \
- REGION(dram_dma, addr, size, 4K) \
- _ = ASSERT(size % 4K == 0, \
- "DRAM DMA buffer should be multiple of smallest page size (4K)!");
+#include <soc/memlayout.h>
SECTIONS
{
diff --git a/src/soc/mediatek/mt8188/include/soc/memlayout.ld b/src/soc/mediatek/mt8188/include/soc/memlayout.ld
index ed3b71be07..3dc386e1f4 100644
--- a/src/soc/mediatek/mt8188/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8188/include/soc/memlayout.ld
@@ -1,19 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
-#include <memlayout.h>
-#include <arch/header.ld>
-/*
- * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
- * It will be returned before starting the ramstage.
- * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
- */
-#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
-#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
-#define DRAM_INIT_CODE(addr, size) \
- REGION(dram_init_code, addr, size, 64K)
-#define DRAM_DMA(addr, size) \
- REGION(dram_dma, addr, size, 4K) \
- _ = ASSERT(size % 4K == 0, \
- "DRAM DMA buffer should be multiple of smallest page size (4K)!");
+#include <soc/memlayout.h>
+
SECTIONS
{
/* MT8188 has 192KB SRAM in total. */
diff --git a/src/soc/mediatek/mt8195/include/soc/memlayout.ld b/src/soc/mediatek/mt8195/include/soc/memlayout.ld
index 06806c508b..ec8fa9c992 100644
--- a/src/soc/mediatek/mt8195/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8195/include/soc/memlayout.ld
@@ -1,26 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/*
- * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
- * It will be returned before starting the ramstage.
- * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
- */
-#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
-#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
-#define DRAM_INIT_CODE(addr, size) \
- REGION(dram_init_code, addr, size, 64K)
-
-#define DRAM_DMA(addr, size) \
- REGION(dram_dma, addr, size, 4K) \
- _ = ASSERT(size % 4K == 0, \
- "DRAM DMA buffer should be multiple of smallest page size (4K)!");
-
-#define EARLY_INIT(addr, size) \
- REGION(early_init_data, addr, size, 4)
+#include <soc/memlayout.h>
SECTIONS
{