diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2023-08-24 15:12:19 +0200 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-31 10:36:39 +0000 |
commit | 7fcd4d58ec7ea2da31c258ba9d8601f086d7f8d8 (patch) | |
tree | 1bddf10cecf4577fee207e0dbc6f7a5c1b10af13 /src/soc | |
parent | 3138faa7cf1b91e0b56ad0b1be6260cf4251a284 (diff) |
device/device.h: Rename busses for clarity
This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc')
27 files changed, 85 insertions, 86 deletions
diff --git a/src/soc/amd/cezanne/xhci.c b/src/soc/amd/cezanne/xhci.c index b0205c6e2a..fc1c11920e 100644 --- a/src/soc/amd/cezanne/xhci.c +++ b/src/soc/amd/cezanne/xhci.c @@ -26,10 +26,10 @@ static const struct sci_source xhci_sci_sources[] = { enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) { - if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + if (dev->upstream->dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; - if (dev->bus->dev->path.pci.devfn != PCIE_ABC_A_DEVFN) + if (dev->upstream->dev->path.pci.devfn != PCIE_ABC_A_DEVFN) return CB_ERR_ARG; if (dev->path.type != DEVICE_PATH_PCI) diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 57b5974e71..bd52d7ca6f 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -96,7 +96,7 @@ static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *de memset(ivhd_entry, 0, sizeof(*ivhd_entry)); ivhd_entry->type = type; - ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8); ivhd_entry->dte_setting = data; *current += sizeof(ivrs_ivhd_generic_t); } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { @@ -104,12 +104,12 @@ static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *de memset(ivhd_entry, 0, sizeof(*ivhd_entry)); ivhd_entry->type = type; - ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->upstream->secondary << 8); ivhd_entry->dte_setting = data; ivhd_entry->reserved1 = 0; ivhd_entry->reserved2 = 0; ivhd_entry->source_dev_id = parent->path.pci.devfn | - (parent->bus->secondary << 8); + (parent->upstream->secondary << 8); *current += sizeof(ivrs_ivhd_alias_t); } @@ -145,7 +145,7 @@ static void add_ivhd_device_entries(struct device *parent, struct device *dev, return; if (dev->path.type == DEVICE_PATH_PCI) { - if ((dev->bus->secondary == nb_bus) && + if ((dev->upstream->secondary == nb_bus) && (dev->path.pci.devfn == 0x0)) *root_level = depth; @@ -154,9 +154,9 @@ static void add_ivhd_device_entries(struct device *parent, struct device *dev, ivrs_add_device_or_bridge(parent, dev, current); } - if (!dev->link_list) + if (!dev->downstream) return; - for (sibling = dev->link_list->children; sibling; sibling = sibling->sibling) + for (sibling = dev->downstream->children; sibling; sibling = sibling->sibling) add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, current, nb_bus); } @@ -173,21 +173,21 @@ static unsigned long acpi_ivhd_misc(unsigned long current, struct device *dev) * Add all possible PCI devices in the domain that can generate transactions * processed by IOMMU. Start with device <bus>:01.0 */ - current = ivhd_dev_range(current, PCI_DEVFN(0, 3) | (dev->link_list->secondary << 8), - 0xff | (dev->link_list->subordinate << 8), 0); + current = ivhd_dev_range(current, PCI_DEVFN(0, 3) | (dev->downstream->secondary << 8), + 0xff | (dev->downstream->subordinate << 8), 0); add_ivhd_device_entries(NULL, dev, 0, -1, &root_level, - ¤t, dev->link_list->secondary); + ¤t, dev->downstream->secondary); res = probe_resource(dev, IOMMU_IOAPIC_IDX); if (res) { /* Describe IOAPIC associated with the IOMMU */ current = acpi_fill_ivrs_ioapic(current, (u8 *)(uintptr_t)res->base, - PCI_DEVFN(0, 1) | (dev->link_list->secondary << 8), 0); + PCI_DEVFN(0, 1) | (dev->downstream->secondary << 8), 0); } /* If the domain has secondary bus as zero then associate HPET & FCH IOAPIC */ - if (dev->link_list->secondary == 0) { + if (dev->downstream->secondary == 0) { /* Describe HPET */ current = ivhd_describe_hpet(current, 0x00, SMBUS_DEVFN); /* Describe FCH IOAPICs */ @@ -212,11 +212,11 @@ static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_ivhd_t *i ivhd_40->flags = ivhd->flags & 0x3f; ivhd_40->length = sizeof(struct acpi_ivrs_ivhd_40); /* BDF <bus>:00.2 */ - ivhd_40->device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivhd_40->device_id = 0x02 | (nb_dev->upstream->secondary << 8); ivhd_40->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); ivhd_40->iommu_base_low = ivhd->iommu_base_low; ivhd_40->iommu_base_high = ivhd->iommu_base_high; - ivhd_40->pci_segment_group = nb_dev->bus->segment_group; + ivhd_40->pci_segment_group = nb_dev->upstream->segment_group; ivhd_40->iommu_info = ivhd->iommu_info; /* For type 40h bits 31:28 and 12:0 are reserved */ ivhd_40->iommu_attributes = ivhd->iommu_feature_info & 0xfffe000; @@ -230,9 +230,9 @@ static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_ivhd_t *i /* Now repeat all the device entries from type 10h */ current_backup = current; - current = acpi_ivhd_misc(current, nb_dev->bus->dev); + current = acpi_ivhd_misc(current, nb_dev->upstream->dev); - if (nb_dev->bus->secondary == 0) { + if (nb_dev->upstream->secondary == 0) { /* Describe EMMC */ if (CONFIG(SOC_AMD_COMMON_BLOCK_EMMC)) { /* PCI_DEVFN(0x13, 1) doesn't exist in the hardware, but it's what the @@ -269,11 +269,11 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_ivhd_t *i ivhd_11->flags = ivhd->flags & 0x3f; ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); /* BDF <bus>:00.2 */ - ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivhd_11->device_id = 0x02 | (nb_dev->upstream->secondary << 8); ivhd_11->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); ivhd_11->iommu_base_low = ivhd->iommu_base_low; ivhd_11->iommu_base_high = ivhd->iommu_base_high; - ivhd_11->pci_segment_group = nb_dev->bus->segment_group; + ivhd_11->pci_segment_group = nb_dev->upstream->segment_group; ivhd_11->iommu_info = ivhd->iommu_info; ivhd11_attr_ptr = (ivhd11_iommu_attr_t *)&ivhd->iommu_feature_info; ivhd_11->iommu_attributes.perf_counters = ivhd11_attr_ptr->perf_counters; @@ -289,7 +289,7 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_ivhd_t *i /* Now repeat all the device entries from type 10h */ current_backup = current; - current = acpi_ivhd_misc(current, nb_dev->bus->dev); + current = acpi_ivhd_misc(current, nb_dev->upstream->dev); ivhd_11->length += (current - current_backup); return acpi_fill_ivrs40(current, ivhd, nb_dev, iommu_dev); @@ -317,8 +317,8 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN)) != NULL) { - nb_dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0)); - iommu_dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 2)); + nb_dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 0)); + iommu_dev = pcidev_path_behind(dev->downstream, PCI_DEVFN(0, 2)); if (!nb_dev) { printk(BIOS_WARNING, "%s: Northbridge device not present!\n", __func__); printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); @@ -334,7 +334,7 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) ivhd->length = sizeof(struct acpi_ivrs_ivhd); /* BDF <bus>:00.2 */ - ivhd->device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivhd->device_id = 0x02 | (nb_dev->upstream->secondary << 8); ivhd->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); ivhd->iommu_base_low = pci_read_config32(iommu_dev, IOMMU_CAP_BASE_LO) & 0xffffc000; ivhd->iommu_base_high = pci_read_config32(iommu_dev, IOMMU_CAP_BASE_HI); @@ -363,7 +363,7 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) ivhd->flags |= ((mmio_x18_value & MMIO_CTRL_HT_TUN_EN) ? IVHD_FLAG_HT_TUN_EN : 0); - ivhd->pci_segment_group = nb_dev->bus->segment_group; + ivhd->pci_segment_group = nb_dev->upstream->segment_group; ivhd->iommu_info = pci_read_config16(iommu_dev, ivhd->capability_offset + 0x10) & 0x1F; diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index b827dd3fad..f17346fedf 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -34,12 +34,12 @@ void amd_pci_domain_scan_bus(struct device *domain) limit = MIN(limit, PCI_BUSES_PER_SEGMENT_GROUP - 1); /* Set bus first number of PCI root */ - domain->link_list->secondary = bus; + domain->downstream->secondary = bus; /* subordinate needs to be the same as secondary before pci_host_bridge_scan_bus call. */ - domain->link_list->subordinate = bus; + domain->downstream->subordinate = bus; /* Tell allocator about maximum PCI bus number in domain */ - domain->link_list->max_subordinate = limit; - domain->link_list->segment_group = segment_group; + domain->downstream->max_subordinate = limit; + domain->downstream->segment_group = segment_group; pci_host_bridge_scan_bus(domain); } @@ -249,12 +249,12 @@ void amd_pci_domain_fill_ssdt(const struct device *domain) /* PCI bus number range in domain */ printk(BIOS_DEBUG, "%s _CRS: adding busses [%x-%x] in segment group %x\n", - acpi_device_name(domain), domain->link_list->secondary, - domain->link_list->max_subordinate, domain->link_list->segment_group); - acpigen_resource_producer_bus_number(domain->link_list->secondary, - domain->link_list->max_subordinate); + acpi_device_name(domain), domain->downstream->secondary, + domain->downstream->max_subordinate, domain->downstream->segment_group); + acpigen_resource_producer_bus_number(domain->downstream->secondary, + domain->downstream->max_subordinate); - if (domain->link_list->secondary == 0 && domain->link_list->segment_group == 0) { + if (domain->downstream->secondary == 0 && domain->downstream->segment_group == 0) { /* ACPI 6.4.2.5 I/O Port Descriptor */ acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1, PCI_IO_CONFIG_PORT_COUNT, 1); @@ -282,7 +282,7 @@ void amd_pci_domain_fill_ssdt(const struct device *domain) } } - if (domain->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_DEBUG, "%s _CRS: adding VGA resource\n", acpi_device_name(domain)); acpigen_resource_producer_mmio(VGA_MMIO_BASE, VGA_MMIO_LIMIT, MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_CACHE); @@ -290,9 +290,8 @@ void amd_pci_domain_fill_ssdt(const struct device *domain) acpigen_write_resourcetemplate_footer(); - acpigen_write_SEG(domain->link_list->segment_group); - acpigen_write_BBN(domain->link_list->secondary); - + acpigen_write_SEG(domain->downstream->segment_group); + acpigen_write_BBN(domain->downstream->secondary); /* Scope */ acpigen_pop_len(); } diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index c076361080..a90fc3e65c 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -280,10 +280,10 @@ static void lpc_enable_children_resources(struct device *dev) { struct device *child; - if (!dev->link_list) + if (!dev->downstream) return; - for (child = dev->link_list->children; child; child = child->sibling) { + for (child = dev->downstream->children; child; child = child->sibling) { if (!child->enabled) continue; if (child->path.type != DEVICE_PATH_PNP) diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index dc3745061d..57e020a4b4 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -18,7 +18,7 @@ static void genoa_domain_read_resources(struct device *domain) amd_pci_domain_read_resources(domain); // We only want to add the DRAM memory map once - if (domain->link_list->secondary == 0 && domain->link_list->segment_group == 0) { + if (domain->downstream->secondary == 0 && domain->downstream->segment_group == 0) { /* 0x1000 is a large enough first index to be sure to not overlap with the resources added by amd_pci_domain_read_resources */ add_opensil_memmap(domain, 0x1000); @@ -27,7 +27,7 @@ static void genoa_domain_read_resources(struct device *domain) static void genoa_domain_set_resources(struct device *domain) { - if (domain->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_DEBUG, "Setting VGA decoding for domain 0x%x\n", domain->path.domain.domain); const union df_vga_en vga_en = { diff --git a/src/soc/amd/glinda/xhci.c b/src/soc/amd/glinda/xhci.c index dad559334d..74e8816e84 100644 --- a/src/soc/amd/glinda/xhci.c +++ b/src/soc/amd/glinda/xhci.c @@ -34,13 +34,13 @@ static const struct sci_source xhci_sci_sources[] = { enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) { - if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + if (dev->upstream->dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; if (dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; - if (dev->bus->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { + if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { if (dev->path.pci.devfn == XHCI0_DEVFN) { *gpe = xhci_sci_sources[0].gpe; return CB_SUCCESS; @@ -48,7 +48,7 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) *gpe = xhci_sci_sources[1].gpe; return CB_SUCCESS; } - } else if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { + } else if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { if (dev->path.pci.devfn == XHCI2_DEVFN && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) { *gpe = xhci_sci_sources[2].gpe; diff --git a/src/soc/amd/mendocino/xhci.c b/src/soc/amd/mendocino/xhci.c index e5649911f4..8f46374fce 100644 --- a/src/soc/amd/mendocino/xhci.c +++ b/src/soc/amd/mendocino/xhci.c @@ -35,13 +35,13 @@ static const struct sci_source xhci_sci_sources[] = { enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) { - if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + if (dev->upstream->dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; if (dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; - if (dev->bus->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { + if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { if (dev->path.pci.devfn == XHCI0_DEVFN) { *gpe = xhci_sci_sources[0].gpe; return CB_SUCCESS; @@ -49,7 +49,7 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) *gpe = xhci_sci_sources[1].gpe; return CB_SUCCESS; } - } else if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { + } else if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { if (dev->path.pci.devfn == XHCI2_DEVFN && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) { *gpe = xhci_sci_sources[2].gpe; diff --git a/src/soc/amd/phoenix/xhci.c b/src/soc/amd/phoenix/xhci.c index 99033f94c6..79d4d079fe 100644 --- a/src/soc/amd/phoenix/xhci.c +++ b/src/soc/amd/phoenix/xhci.c @@ -39,13 +39,13 @@ static const struct sci_source xhci_sci_sources[] = { enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) { - if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + if (dev->upstream->dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; if (dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; - if (dev->bus->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { + if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) { if (dev->path.pci.devfn == XHCI0_DEVFN) { *gpe = xhci_sci_sources[0].gpe; return CB_SUCCESS; @@ -55,7 +55,7 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) } } - if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { + if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { if (dev->path.pci.devfn == USB4_XHCI0_DEVFN) { *gpe = xhci_sci_sources[2].gpe; return CB_SUCCESS; diff --git a/src/soc/amd/picasso/xhci.c b/src/soc/amd/picasso/xhci.c index 84b3a2b82d..a238916b71 100644 --- a/src/soc/amd/picasso/xhci.c +++ b/src/soc/amd/picasso/xhci.c @@ -26,10 +26,10 @@ static const struct sci_source xhci_sci_sources[] = { enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) { - if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + if (dev->upstream->dev->path.type != DEVICE_PATH_PCI) return CB_ERR_ARG; - if (dev->bus->dev->path.pci.devfn != PCIE_GPP_A_DEVFN) + if (dev->upstream->dev->path.pci.devfn != PCIE_GPP_A_DEVFN) return CB_ERR_ARG; if (dev->path.type != DEVICE_PATH_PCI) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index b95c4cdf2e..a92c3b506d 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -52,9 +52,9 @@ static void read_resources(struct device *dev) static void create_vga_resource(struct device *dev) { - if (!dev->link_list) + if (!dev->downstream) return; - if (!(dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)) + if (!(dev->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA)) return; printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); @@ -67,8 +67,8 @@ static void set_resources(struct device *dev) /* do we need this? */ create_vga_resource(dev); - if (dev->link_list && dev->link_list->children) - assign_resources(dev->link_list); + if (dev->downstream && dev->downstream->children) + assign_resources(dev->downstream); } static void northbridge_init(struct device *dev) diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index d02e8843f2..ff3e7097ff 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -226,12 +226,12 @@ static void ecam0_init(struct device *dev) * Search for missing devices on BUS 1. * Only required for ARI capability programming. */ - ecam0_fix_missing_devices(bridge->link_list); + ecam0_fix_missing_devices(bridge->downstream); /* Program secure ARI capability on bus 1 */ child_last = NULL; for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) { - child = pcidev_path_behind(bridge->link_list, i); + child = pcidev_path_behind(bridge->downstream, i); if (!child || !child->enabled) continue; @@ -250,7 +250,7 @@ static void ecam0_init(struct device *dev) /* Program insecure ARI capability on bus 1 */ child_last = NULL; for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) { - child = pcidev_path_behind(bridge->link_list, i); + child = pcidev_path_behind(bridge->downstream, i); if (!child) continue; config = child->chip_info; @@ -281,7 +281,7 @@ static void ecam0_init(struct device *dev) /* Enable / disable devices and functions on bus 1 */ for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) { - child = pcidev_path_behind(bridge->link_list, i); + child = pcidev_path_behind(bridge->downstream, i); config = child ? child->chip_info : NULL; if (child && child->enabled && ((config && !config->secure) || !config)) @@ -293,7 +293,7 @@ static void ecam0_init(struct device *dev) /* Apply IRQ on PCI devices */ /* UUA */ for (i = 0; i < 4; i++) { - child = pcidev_path_behind(bridge->link_list, + child = pcidev_path_behind(bridge->downstream, PCI_DEVFN(8, i)); if (!child) continue; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 469b9be8d1..15780d0971 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -478,7 +478,7 @@ static void parse_devicetree(FSP_S_CONFIG *silconfig) return; } /* Only disable bus 0 devices. */ - for (dev = dev->bus->children; dev; dev = dev->sibling) { + for (dev = dev->upstream->children; dev; dev = dev->sibling) { if (!dev->enabled) disable_dev(dev, silconfig); } diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index a0df97cdf7..2e3728057d 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -117,7 +117,7 @@ static void write_pci_config_irqs(void) continue; current_bdf = irq_dev->path.pci.devfn | - irq_dev->bus->secondary << 8; + irq_dev->upstream->secondary << 8; /* * Step 1: Get the INT_PIN and device structure to look for @@ -132,7 +132,7 @@ static void write_pci_config_irqs(void) original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); parent_bdf = targ_dev->path.pci.devfn - | targ_dev->bus->secondary << 8; + | targ_dev->upstream->secondary << 8; device_num = PCI_SLOT(parent_bdf); if (ir->pcidev[device_num] == 0) { diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index 39f95425db..a6ae454d06 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -144,7 +144,7 @@ static enum acpi_device_sleep_states get_min_sleep_state( case DEVICE_PATH_PCI: /* skip external buses*/ - if ((dev->bus->secondary != 0) || (!states_arr)) + if ((dev->upstream->secondary != 0) || (!states_arr)) return ACPI_DEVICE_SLEEP_NONE; for (size_t i = 0; i < size; i++) if (states_arr[i].pci_dev == dev->path.pci.devfn) diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 994ef9bcb8..dbd982b593 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -102,10 +102,10 @@ static void pch_lpc_set_child_resources(struct device *dev) { struct device *child; - if (!dev->link_list) + if (!dev->downstream) return; - for (child = dev->link_list->children; child; child = child->sibling) + for (child = dev->downstream->children; child; child = child->sibling) pch_lpc_loop_resources(child); } diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 39c82b11f2..3a7c8b4afc 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -140,7 +140,7 @@ pcie_rtd3_acpi_method_on(unsigned int pcie_rp, enum pcie_rp_type rp_type, const struct device *dev) { - const struct device *parent = dev->bus->dev; + const struct device *parent = dev->upstream->dev; acpigen_write_method_serialized("_ON", 0); @@ -224,7 +224,7 @@ pcie_rtd3_acpi_method_off(int pcie_rp, const struct device *dev) { - const struct device *parent = dev->bus->dev; + const struct device *parent = dev->upstream->dev; acpigen_write_method_serialized("_OFF", 0); @@ -385,7 +385,7 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev); static const char *const power_res_states[] = {"_PR0"}; - const struct device *parent = dev->bus->dev; + const struct device *parent = dev->upstream->dev; const char *scope = acpi_device_path(parent); const struct opregion opregion = OPREGION("PXCS", PCI_CONFIG, 0, 0xff); const struct fieldlist fieldlist[] = { diff --git a/src/soc/intel/common/block/usb4/pcie.c b/src/soc/intel/common/block/usb4/pcie.c index f2414ccb12..c066647d1a 100644 --- a/src/soc/intel/common/block/usb4/pcie.c +++ b/src/soc/intel/common/block/usb4/pcie.c @@ -19,7 +19,7 @@ static void usb4_pcie_acpi_fill_ssdt(const struct device *dev) int port_id; /* Get parent PCI device */ - parent = dev->bus->dev; + parent = dev->upstream->dev; if (!parent) { printk(BIOS_ERR, "%s: Unable to find parent device\n", __func__); return; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index ff6fbf0957..03ed578e27 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -92,8 +92,8 @@ void usb_xhci_disable_unused(bool (*ext_usb_xhci_en_cb)(unsigned int port_type, return; } - while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) { - while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { + while ((hub = dev_bus_each_child(xhci->downstream, hub)) != NULL) { + while ((port = dev_bus_each_child(hub->downstream, port)) != NULL) { enable = true; config = config_of(port); if (config->type == UPC_TYPE_INTERNAL) { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 7ebca1eb94..ae923d7c0e 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -275,7 +275,7 @@ static u8 dnv_get_int_line(struct device *irq_dev) /* Swizzle this device if needed */ config = targ_dev->chip_info; - parent_bdf = targ_dev->path.pci.devfn | targ_dev->bus->secondary << 8; + parent_bdf = targ_dev->path.pci.devfn | targ_dev->upstream->secondary << 8; if (is_dnv_swizzled_rp(parent_bdf) && irq_dev != targ_dev) { swiz_int_pin = dnv_get_swizzled_pin(config, parent_bdf, new_int_pin); printk(BIOS_DEBUG, "%s: dnv swizzle %s from %c to %c\n", __func__, @@ -387,7 +387,7 @@ static void pch_pirq_init(struct device *dev) int_line = dnv_get_int_line(irq_dev); printk(BIOS_DEBUG, "%s: %02x:%02x.%d pin %d int line %d\n", __func__, - irq_dev->bus->secondary, devfn >> 3, devfn & 0x7, int_pin, int_line); + irq_dev->upstream->secondary, devfn >> 3, devfn & 0x7, int_pin, int_line); pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); } diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index c3c478544e..971fa3360d 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -760,7 +760,7 @@ static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg, for (dev = all_devices; dev; dev = dev->next) { if (!(is_dev_enabled(dev) && dev->path.type == DEVICE_PATH_PCI && - dev->bus->secondary == 0)) + dev->upstream->secondary == 0)) continue; if (dev->path.pci.devfn == PCI_DEVFN_ROOT) { diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index f471edb960..ea091ce0ac 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -94,7 +94,7 @@ const char *soc_acpi_name(const struct device *dev) return NULL; /* Match functions 0 and 1 for possible GPUs on a secondary bus */ - if (dev->bus && dev->bus->secondary > 0) { + if (dev->upstream && dev->upstream->secondary > 0) { switch (PCI_FUNC(dev->path.pci.devfn)) { case 0: return "DEV0"; case 1: return "DEV1"; diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 845e968a62..144dba1665 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -78,7 +78,7 @@ void iio_pci_domain_scan_bus(struct device *dev) bus->max_subordinate = sr->BusLimit; printk(BIOS_SPEW, "Scanning IIO stack %d: busses %x-%x\n", dev->path.domain.domain, - dev->link_list->secondary, dev->link_list->max_subordinate); + dev->downstream->secondary, dev->downstream->max_subordinate); pci_host_bridge_scan_bus(dev); } @@ -116,14 +116,14 @@ void attach_iio_stacks(struct device *dev) if (!is_pcie_iio_stack_res(ri)) { if (CONFIG(HAVE_IOAT_DOMAINS)) - soc_create_ioat_domains(dn, dev->bus, ri); + soc_create_ioat_domains(dn, dev->upstream, ri); continue; } struct device_path path; path.type = DEVICE_PATH_DOMAIN; path.domain.domain = dn.domain_path; - struct device *iio_domain = alloc_dev(dev->bus, &path); + struct device *iio_domain = alloc_dev(dev->upstream, &path); if (iio_domain == NULL) die("%s: out of memory.\n", __func__); iio_domain->ops = &iio_pcie_domain_ops; diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 2c19ed1198..8b24ba2b52 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -46,7 +46,7 @@ void uncore_fill_ssdt(const struct device *device) struct iiostack_resource stack_info = {0}; /* Only add RTxx entries once. */ - if (device->bus->secondary != 0 || device->bus->segment_group != 0) + if (device->upstream->secondary != 0 || device->upstream->segment_group != 0) return; get_iiostack_info(&stack_info); diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index dfbd878793..2e2b14a2cc 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -59,7 +59,7 @@ void uncore_fill_ssdt(const struct device *device) const IIO_UDS *hob = get_iio_uds(); /* Only add RTxx entries once. */ - if (device->bus->secondary != 0) + if (device->upstream->secondary != 0) return; for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) { diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index cb7fe1daf1..a48302cf2e 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -341,7 +341,7 @@ void uncore_fill_ssdt(const struct device *device) bool stack_enabled; /* Only add RTxx entries once. */ - if (device->bus->secondary != 0) + if (device->upstream->secondary != 0) return; /* @@ -502,7 +502,7 @@ unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) for (cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) - || (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + || (cpu->upstream->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { continue; } if (!cpu->enabled) diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 1b232ea208..ddc6e8206f 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -192,7 +192,7 @@ static void mc_add_dram_resources(struct device *dev, int *res_count) struct range_entry fsp_mem; /* Only add dram resources once. */ - if (dev->bus->secondary != 0 || dev->bus->segment_group != 0) + if (dev->upstream->secondary != 0 || dev->upstream->segment_group != 0) return; /* Read in the MAP registers and report their values. */ diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index e2b47329ac..75b281bd8d 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -225,7 +225,7 @@ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, uint32_t pcie_seg, bool is_atsr, bool *first) { - const uint32_t bus = bridge_dev->bus->secondary; + const uint32_t bus = bridge_dev->upstream->secondary; const uint32_t dev = PCI_SLOT(bridge_dev->path.pci.devfn); const uint32_t func = PCI_FUNC(bridge_dev->path.pci.devfn); |