summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-12-11 17:12:32 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-12-14 10:40:51 +0000
commit68cf57cf33141edcc8b4b1250b099884e0553457 (patch)
treecc7a8d69a6fa3fe6e802fbe31f325cfd40e40d8c /src/soc
parent950cdbc3e25f021cb71693fb7c27b0588da1233d (diff)
soc/intel/skylake: Drop always-zero ProbelessTrace dt setting
This seems to be a debugging option. Since unset devicetree options default to zero, drop the setting. If it is needed in the future, a user-visible Kconfig option would probably make more sense. Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/skylake/chip.h3
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c2
2 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 4d92410b65..f4744c9631 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -90,9 +90,6 @@ struct soc_intel_skylake_config {
/* Whether to ignore VT-d support of the SKU */
int ignore_vtd;
- /* Probeless Trace function */
- u8 ProbelessTrace;
-
/*
* System Agent dynamic frequency configuration
* When enabled memory will be trained at two different frequencies.
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 79fb46425d..c826187c4b 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -216,7 +216,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->MmioSize = 0x800; /* 2GB in MB */
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
- m_cfg->ProbelessTrace = config->ProbelessTrace;
+ m_cfg->ProbelessTrace = 0;
m_cfg->SaGv = config->SaGv;
m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
m_cfg->RMT = config->Rmt;