diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-09-22 21:56:17 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-04-22 22:44:57 +0000 |
| commit | 305b6488e4cd4adfc7427938928dca51f4d70dd7 (patch) | |
| tree | 73f6b0a2d96e14e577e0026590dcb5858f9c9ff8 /src/soc | |
| parent | 348f2a63707cc1711cc836837fc7f5b36b2e0553 (diff) | |
soc/intel/cannonlake: set MSR LT_LOCK_MEMORY at end of POST
FSP does not set the MSR LT_LOCK_MEMORY when SkipMpInit=1. Therefore,
set LT_LOCK_MEMORY at end of POST, when native MP init is used, to
protect SMM in accordance to Intel BWG.
Test on clevo/cml-u: chipsec says LT_LOCK_MEMORY is locked.
Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36356
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/finalize.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 8387bb86f7..9b56c0ada2 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -6,6 +6,7 @@ #include <console/post_codes.h> #include <cpu/x86/smm.h> #include <device/pci.h> +#include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> @@ -69,6 +70,14 @@ static void pch_finalize(void) pch_handle_sideband(config); pmc_clear_pmcon_sts(); + + /* + * Lock chipset memory registers to protect SMM. + * When SkipMpInit=0, this is done by FSP. + */ + if (!CONFIG(USE_INTEL_FSP_MP_INIT)) + cpu_lt_lock_memory(); + } static void soc_finalize(void *unused) |