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authorJamie Ryu <jamie.m.ryu@intel.com>2024-09-18 14:54:26 -0700
committerSubrata Banik <subratabanik@google.com>2024-09-23 16:31:57 +0000
commit279946792dd83eece29011a11a463a05a30fda7f (patch)
tree042343ecc21a599cb9a4c2e70a9a78206342f9a4 /src/soc
parent183a17e42f1d699ad0fb5f6378663d346ffcb8da (diff)
soc/intel/pantherlake: Disable Total Memory Encryption
TME, Total Memory Encryption will be enabled once the feature is fully verified with Panther Lake. Change-Id: I600c8a499df3b8796df35813422d0e89f67cc630 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84418 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/pantherlake/Kconfig2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index fb6c48bfff..94104cca55 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -9,7 +9,6 @@ config SOC_INTEL_PANTHERLAKE_BASE
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_VOLTAGE
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
- select CPU_SUPPORTS_INTEL_TME
select CPU_SUPPORTS_PM_TIMER_EMULATION
select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS
select DEFAULT_X2APIC_LATE_WORKAROUND
@@ -102,7 +101,6 @@ config SOC_INTEL_PANTHERLAKE_BASE
select SOC_QDF_DYNAMIC_READ_PMC
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
- select TME_KEY_REGENERATION_ON_WARM_BOOT
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_202302_BINDING