arch/x86/ioapic: use uintptr_t for IOAPIC base address

Use uintptr_t for the IOAPIC base parameter of the various IOAPIC-
related functions to avoid needing type casts in the callers. This also
allows dropping the VIO_APIC_VADDR define and consistently use the
IO_APIC_ADDR define instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I912943e923ff092708e90138caa5e1daf269a69f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>

8 files changed, 13 insertions, 13 deletions

diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c
index bd52d7ca6f..74c5c39b52 100644
--- a/src/soc/amd/common/block/acpi/ivrs.c
+++ b/src/soc/amd/common/block/acpi/ivrs.c
@@ -16,7 +16,7 @@
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 
-static unsigned long acpi_fill_ivrs_ioapic(unsigned long current, void *ioapic_base,
+static unsigned long acpi_fill_ivrs_ioapic(unsigned long current, uintptr_t ioapic_base,
 					    uint16_t src_devid, uint8_t dte_setting)
 {
 	ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current;
@@ -182,7 +182,7 @@ static unsigned long acpi_ivhd_misc(unsigned long current, struct device *dev)
 	res = probe_resource(dev, IOMMU_IOAPIC_IDX);
 	if (res) {
 		/* Describe IOAPIC associated with the IOMMU */
-		current = acpi_fill_ivrs_ioapic(current, (u8 *)(uintptr_t)res->base,
+		current = acpi_fill_ivrs_ioapic(current, (uintptr_t)res->base,
 				      PCI_DEVFN(0, 1) | (dev->downstream->secondary << 8), 0);
 	}
 
@@ -191,7 +191,7 @@ static unsigned long acpi_ivhd_misc(unsigned long current, struct device *dev)
 		/* Describe HPET */
 		current = ivhd_describe_hpet(current, 0x00, SMBUS_DEVFN);
 		/* Describe FCH IOAPICs */
-		current = acpi_fill_ivrs_ioapic(current, VIO_APIC_VADDR,
+		current = acpi_fill_ivrs_ioapic(current, IO_APIC_ADDR,
 				      SMBUS_DEVFN, dte_setting);
 	}
 
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index a90fc3e65c..2392d5f3e8 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -45,7 +45,7 @@ void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
 static void fch_ioapic_init(void)
 {
 	fch_enable_ioapic_decode();
-	register_new_ioapic_gsi0(VIO_APIC_VADDR);
+	register_new_ioapic_gsi0(IO_APIC_ADDR);
 }
 
 static void lpc_init(struct device *dev)
diff --git a/src/soc/amd/common/block/root_complex/ioapic.c b/src/soc/amd/common/block/root_complex/ioapic.c
index cdeb53239b..e183428ca5 100644
--- a/src/soc/amd/common/block/root_complex/ioapic.c
+++ b/src/soc/amd/common/block/root_complex/ioapic.c
@@ -13,5 +13,5 @@ void amd_pci_domain_init(struct device *domain)
 	if (!res)
 		return;
 
-	register_new_ioapic((void *)(uintptr_t)res->base);
+	register_new_ioapic((uintptr_t)res->base);
 }
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index a92c3b506d..b51601ba02 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -73,7 +73,7 @@ static void set_resources(struct device *dev)
 
 static void northbridge_init(struct device *dev)
 {
-	register_new_ioapic((u8 *)IO_APIC2_ADDR);
+	register_new_ioapic(IO_APIC2_ADDR);
 }
 
 /* Used by \_SB.PCI0._CRS */
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c
index 9aaca215b8..ecd66fa626 100644
--- a/src/soc/intel/broadwell/pch/lpc.c
+++ b/src/soc/intel/broadwell/pch/lpc.c
@@ -31,9 +31,9 @@ static void pch_enable_ioapic(struct device *dev)
 
 	/* affirm full set of redirection table entries ("write once") */
 	/* PCH-LP has 40 redirection entries */
-	ioapic_set_max_vectors(VIO_APIC_VADDR, 40);
+	ioapic_set_max_vectors(IO_APIC_ADDR, 40);
 
-	register_new_ioapic_gsi0(VIO_APIC_VADDR);
+	register_new_ioapic_gsi0(IO_APIC_ADDR);
 }
 
 #define ACPI_SCI_IRQ	9
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index ed76049b6d..9a7165baaf 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -395,9 +395,9 @@ void lpc_disable_clkrun(void)
 void pch_enable_ioapic(void)
 {
 	/* affirm full set of redirection table entries ("write once") */
-	ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR);
+	ioapic_set_max_vectors(IO_APIC_ADDR, PCH_REDIR_ETR);
 
-	register_new_ioapic_gsi0((void *)IO_APIC_ADDR);
+	register_new_ioapic_gsi0(IO_APIC_ADDR);
 }
 
 static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = {
diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c
index ae923d7c0e..7dc971ea92 100644
--- a/src/soc/intel/denverton_ns/lpc.c
+++ b/src/soc/intel/denverton_ns/lpc.c
@@ -32,9 +32,9 @@
 static void pch_enable_ioapic(struct device *dev)
 {
 	/* affirm full set of redirection table entries ("write once") */
-	ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR);
+	ioapic_set_max_vectors(IO_APIC_ADDR, PCH_REDIR_ETR);
 
-	register_new_ioapic_gsi0((void *)IO_APIC_ADDR);
+	register_new_ioapic_gsi0(IO_APIC_ADDR);
 }
 
 /* interrupt router lookup for internal devices */
diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index 5ee9087040..b4856120a7 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -283,7 +283,7 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket,
 	if (socket == 0 && stack == IioStack0) {
 		union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf();
 		printk(BIOS_DEBUG, "    [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, "
-		       "PCI Path: 0x%x, 0x%x\n", get_ioapic_id(VIO_APIC_VADDR), ioapic_bdf.bus,
+		       "PCI Path: 0x%x, 0x%x\n", get_ioapic_id(IO_APIC_ADDR), ioapic_bdf.bus,
 		       ioapic_bdf.dev, ioapic_bdf.fn);
 		current += acpi_create_dmar_ds_ioapic_from_hw(current,
 				IO_APIC_ADDR, ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn);