diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-04-21 16:12:22 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-22 16:08:53 +0000 |
| commit | e8a21e7a623a99ef067b45e6fe5316f83068524d (patch) | |
| tree | 963550fea2bee1849d44ad8d25e12eaa4e13828c /src/soc | |
| parent | b5d8cf8d1c66981ce5d17aa8eaf9f2495983247f (diff) | |
soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFN
Since it's an internal bus, it's PCIE_ABC_C_DEVFN and not
PCIE_GPP_C_DEVFN. This also makes it consistent with the rest of the
internal PCI buses.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ica8b666161c3cd3b0b4a29f8a4b0aff473b4d833
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/pci_devs.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/glinda/include/soc/pci_devs.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/glinda/xhci.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/include/soc/pci_devs.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/xhci.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/phoenix/include/soc/pci_devs.h | 2 |
6 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/amd/cezanne/include/soc/pci_devs.h b/src/soc/amd/cezanne/include/soc/pci_devs.h index 8f5793bbb9..2337e0c6cf 100644 --- a/src/soc/amd/cezanne/include/soc/pci_devs.h +++ b/src/soc/amd/cezanne/include/soc/pci_devs.h @@ -108,7 +108,7 @@ #define SATA1_DEVFN PCI_DEVFN(SATA1_DEV, SATA1_FUNC) #define PCIE_ABC_C_FUNC 3 -#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) /* SMBUS */ diff --git a/src/soc/amd/glinda/include/soc/pci_devs.h b/src/soc/amd/glinda/include/soc/pci_devs.h index 4e0bf9dcb2..a37d3eeb14 100644 --- a/src/soc/amd/glinda/include/soc/pci_devs.h +++ b/src/soc/amd/glinda/include/soc/pci_devs.h @@ -86,7 +86,7 @@ #define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) #define PCIE_ABC_C_FUNC 3 -#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define XHCI2_DEV 0x0 diff --git a/src/soc/amd/glinda/xhci.c b/src/soc/amd/glinda/xhci.c index 78ca94ff4d..dad559334d 100644 --- a/src/soc/amd/glinda/xhci.c +++ b/src/soc/amd/glinda/xhci.c @@ -48,7 +48,7 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) *gpe = xhci_sci_sources[1].gpe; return CB_SUCCESS; } - } else if (dev->bus->dev->path.pci.devfn == PCIE_GPP_C_DEVFN) { + } else if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { if (dev->path.pci.devfn == XHCI2_DEVFN && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) { *gpe = xhci_sci_sources[2].gpe; diff --git a/src/soc/amd/mendocino/include/soc/pci_devs.h b/src/soc/amd/mendocino/include/soc/pci_devs.h index 14c8300891..2c81a5bcb7 100644 --- a/src/soc/amd/mendocino/include/soc/pci_devs.h +++ b/src/soc/amd/mendocino/include/soc/pci_devs.h @@ -84,7 +84,7 @@ #define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) #define PCIE_ABC_C_FUNC 3 -#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define XHCI2_DEV 0x0 diff --git a/src/soc/amd/mendocino/xhci.c b/src/soc/amd/mendocino/xhci.c index 720cc765ad..e5649911f4 100644 --- a/src/soc/amd/mendocino/xhci.c +++ b/src/soc/amd/mendocino/xhci.c @@ -49,7 +49,7 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) *gpe = xhci_sci_sources[1].gpe; return CB_SUCCESS; } - } else if (dev->bus->dev->path.pci.devfn == PCIE_GPP_C_DEVFN) { + } else if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { if (dev->path.pci.devfn == XHCI2_DEVFN && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) { *gpe = xhci_sci_sources[2].gpe; diff --git a/src/soc/amd/phoenix/include/soc/pci_devs.h b/src/soc/amd/phoenix/include/soc/pci_devs.h index 0dde0ba431..cd7ad08f64 100644 --- a/src/soc/amd/phoenix/include/soc/pci_devs.h +++ b/src/soc/amd/phoenix/include/soc/pci_devs.h @@ -104,7 +104,7 @@ #define GFX_IPU_DEVFN PCI_DEVFN(GFX_IPU_DEV, GFX_IPU_FUNC) #define PCIE_ABC_C_FUNC 3 -#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define USB4_XHCI0_DEV 0x0 |